文件名称:dds_using_FPGA
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- 上传时间：2012-11-16
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文件大小：98.28kb
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利用FPGA实现DDS经过编译没有错误。编译环境为QuartusII7.2，该环境集成了IP核，可以提高开发效率。-FPGA realization of the use of DDS compiled no errors. Compiler environment QuartusII7.2, the environment integrated IP core, can improve the development efficiency.
相关搜索： cos.mif sin.mif
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下载文件列表
dds_using_FPGA/cos.mif
dds_using_FPGA/cos_rom.bsf
dds_using_FPGA/cos_rom.inc
dds_using_FPGA/cos_rom.tdf
dds_using_FPGA/db/add_sub_6fg.tdf
dds_using_FPGA/db/altsyncram_3u41.tdf
dds_using_FPGA/db/altsyncram_4pi2.tdf
dds_using_FPGA/db/altsyncram_90m1.tdf
dds_using_FPGA/db/altsyncram_9pi2.tdf
dds_using_FPGA/db/altsyncram_b431.tdf
dds_using_FPGA/db/altsyncram_ut41.tdf
dds_using_FPGA/db/altsyncram_vpl1.tdf
dds_using_FPGA/db/dds.db_info
dds_using_FPGA/db/dds.eco.cdb
dds_using_FPGA/db/dds.sld_design_entry.sci
dds_using_FPGA/db/decode_ogi.tdf
dds_using_FPGA/db/mux_ogc.tdf
dds_using_FPGA/dds.asm.rpt
dds_using_FPGA/dds.done
dds_using_FPGA/dds.fit.rpt
dds_using_FPGA/dds.fit.smsg
dds_using_FPGA/dds.fit.summary
dds_using_FPGA/dds.flow.rpt
dds_using_FPGA/dds.map.rpt
dds_using_FPGA/dds.map.summary
dds_using_FPGA/dds.pin
dds_using_FPGA/dds.qpf
dds_using_FPGA/dds.qsf
dds_using_FPGA/dds.qws
dds_using_FPGA/dds.tan.rpt
dds_using_FPGA/dds.tan.summary
dds_using_FPGA/dds_assignment_defaults.qdf
dds_using_FPGA/dds_lut.bdf
dds_using_FPGA/dds_lut.bsf
dds_using_FPGA/dds_lut.v
dds_using_FPGA/mux4.bsf
dds_using_FPGA/mux4.inc
dds_using_FPGA/mux4.tdf
dds_using_FPGA/ram.bsf
dds_using_FPGA/ram.inc
dds_using_FPGA/ram.tdf
dds_using_FPGA/sin.mif
dds_using_FPGA/sin_rom.bsf
dds_using_FPGA/sin_rom.inc
dds_using_FPGA/sin_rom.tdf
dds_using_FPGA/square.bsf
dds_using_FPGA/square.inc
dds_using_FPGA/square.tdf
dds_using_FPGA/squra.mif
dds_using_FPGA/db
dds_using_FPGA
dds_using_FPGA/cos_rom.bsf
dds_using_FPGA/cos_rom.inc
dds_using_FPGA/cos_rom.tdf
dds_using_FPGA/db/add_sub_6fg.tdf
dds_using_FPGA/db/altsyncram_3u41.tdf
dds_using_FPGA/db/altsyncram_4pi2.tdf
dds_using_FPGA/db/altsyncram_90m1.tdf
dds_using_FPGA/db/altsyncram_9pi2.tdf
dds_using_FPGA/db/altsyncram_b431.tdf
dds_using_FPGA/db/altsyncram_ut41.tdf
dds_using_FPGA/db/altsyncram_vpl1.tdf
dds_using_FPGA/db/dds.db_info
dds_using_FPGA/db/dds.eco.cdb
dds_using_FPGA/db/dds.sld_design_entry.sci
dds_using_FPGA/db/decode_ogi.tdf
dds_using_FPGA/db/mux_ogc.tdf
dds_using_FPGA/dds.asm.rpt
dds_using_FPGA/dds.done
dds_using_FPGA/dds.fit.rpt
dds_using_FPGA/dds.fit.smsg
dds_using_FPGA/dds.fit.summary
dds_using_FPGA/dds.flow.rpt
dds_using_FPGA/dds.map.rpt
dds_using_FPGA/dds.map.summary
dds_using_FPGA/dds.pin
dds_using_FPGA/dds.qpf
dds_using_FPGA/dds.qsf
dds_using_FPGA/dds.qws
dds_using_FPGA/dds.tan.rpt
dds_using_FPGA/dds.tan.summary
dds_using_FPGA/dds_assignment_defaults.qdf
dds_using_FPGA/dds_lut.bdf
dds_using_FPGA/dds_lut.bsf
dds_using_FPGA/dds_lut.v
dds_using_FPGA/mux4.bsf
dds_using_FPGA/mux4.inc
dds_using_FPGA/mux4.tdf
dds_using_FPGA/ram.bsf
dds_using_FPGA/ram.inc
dds_using_FPGA/ram.tdf
dds_using_FPGA/sin.mif
dds_using_FPGA/sin_rom.bsf
dds_using_FPGA/sin_rom.inc
dds_using_FPGA/sin_rom.tdf
dds_using_FPGA/square.bsf
dds_using_FPGA/square.inc
dds_using_FPGA/square.tdf
dds_using_FPGA/squra.mif
dds_using_FPGA/db
dds_using_FPGA
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