文件名称:Examples
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- 上传时间：2012-11-16
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文件大小：23.96kb
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几个简单的verilog代码，推荐用modelsim工具学习-A few simple Verilog code, recommended by ModelSim tools to learn
(系统自动生成,下载前可以参看下载内容)
下载文件列表
Examples/abc_100.v
Examples/analog.spj
Examples/analog.v
Examples/code_coverage.spj
Examples/code_coverage.v
Examples/code_coverage2.spj
Examples/design.lib
Examples/design.sdf
Examples/design.sym
Examples/design.v
Examples/design1
Examples/design2
Examples/faulttst.v
Examples/fltsim.spj
Examples/gate.spj
Examples/rtl.sym
Examples/rtl_.spj
Examples/rtl_err.spj
Examples/stimulus.v
Examples/stimulus.v1
Examples/testbench.v
Examples/testbench2.v
Examples/vend.gv
Examples/vend.v
Examples/venderr.v
Examples/vending.fsm
Examples/vending.spj
Examples/vending.sym
Examples/vending.v
Examples/vending_testbench.v
Examples/vendtest.v
Examples
Examples/analog.spj
Examples/analog.v
Examples/code_coverage.spj
Examples/code_coverage.v
Examples/code_coverage2.spj
Examples/design.lib
Examples/design.sdf
Examples/design.sym
Examples/design.v
Examples/design1
Examples/design2
Examples/faulttst.v
Examples/fltsim.spj
Examples/gate.spj
Examples/rtl.sym
Examples/rtl_.spj
Examples/rtl_err.spj
Examples/stimulus.v
Examples/stimulus.v1
Examples/testbench.v
Examples/testbench2.v
Examples/vend.gv
Examples/vend.v
Examples/venderr.v
Examples/vending.fsm
Examples/vending.spj
Examples/vending.sym
Examples/vending.v
Examples/vending_testbench.v
Examples/vendtest.v
Examples
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