文件名称:LCD_1602
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- 上传时间:2012-11-16
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文件大小:504kb
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液晶屏lcd1602的使用历程,在actel的fusion系列FPGA中综合通过-LCD lcd1602 the use of the course, in the Actel FPGA series of fusion integrated through
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下载文件列表
LCD_1602/designer/impl1/Clock_Gen.ide_des
LCD_1602/designer/impl1/designer.log
LCD_1602/designer/impl1/designer_genhdl.log
LCD_1602/designer/impl1/LCD_Driver.ide_des
LCD_1602/designer/impl1/LCD_Top.adb
LCD_1602/designer/impl1/LCD_Top.dtf/verify.log
LCD_1602/designer/impl1/LCD_Top.ide_des
LCD_1602/designer/impl1/LCD_Top.pdb
LCD_1602/designer/impl1/LCD_Top.pdb.depends
LCD_1602/designer/impl1/LCD_Top.tcl
LCD_1602/designer/impl1/LCD_Top_ba.sdf
LCD_1602/designer/impl1/LCD_Top_ba.v
LCD_1602/designer/impl1/LED.ide_des
LCD_1602/designer/impl1/PLL_1M.ide_des
LCD_1602/hdl/Clock_Gen.v
LCD_1602/hdl/LCD_Driver.v
LCD_1602/hdl/LCD_Top.v
LCD_1602/hdl/LED.v
LCD_1602/LCD_1602.prj
LCD_1602/simulation/modelsim.ini
LCD_1602/simulation/modelsim.ini.sav
LCD_1602/smartgen/PLL_1M/PLL_1M.cxf
LCD_1602/smartgen/PLL_1M/PLL_1M.gen
LCD_1602/smartgen/PLL_1M/PLL_1M.log
LCD_1602/smartgen/PLL_1M/PLL_1M.v
LCD_1602/smartgen/PLL_1M_work.ixf
LCD_1602/smartgen/smartgen.aws
LCD_1602/synthesis/.recordref
LCD_1602/synthesis/backup/LCD_Top.srr
LCD_1602/synthesis/LCD_Top.areasrr
LCD_1602/synthesis/LCD_Top.edn
LCD_1602/synthesis/LCD_Top.map
LCD_1602/synthesis/LCD_Top.pdc
LCD_1602/synthesis/LCD_Top.sdf
LCD_1602/synthesis/LCD_Top.so
LCD_1602/synthesis/LCD_Top.srd
LCD_1602/synthesis/LCD_Top.srm
LCD_1602/synthesis/LCD_Top.srr
LCD_1602/synthesis/LCD_Top.srs
LCD_1602/synthesis/LCD_Top.szr
LCD_1602/synthesis/LCD_Top.tlg
LCD_1602/synthesis/LCD_Top_drc.rpt
LCD_1602/synthesis/LCD_Top_sdc.sdc
LCD_1602/synthesis/LCD_Top_syn.prj
LCD_1602/synthesis/run_options.txt
LCD_1602/synthesis/stdout.log
LCD_1602/synthesis/syntmp/LCD_Top.plg
LCD_1602/synthesis/traplog.tlg
LCD_1602/viewdraw/vf/project.lst
LCD_1602/viewdraw/viewdraw.ini
LCD_1602/designer/impl1/LCD_Top.dtf
LCD_1602/designer/impl1/simulation
LCD_1602/designer/impl1
LCD_1602/smartgen/PLL_1M
LCD_1602/synthesis/backup
LCD_1602/synthesis/coreip
LCD_1602/synthesis/syntmp
LCD_1602/viewdraw/sch
LCD_1602/viewdraw/sym
LCD_1602/viewdraw/vf
LCD_1602/viewdraw/wir
LCD_1602/component
LCD_1602/constraint
LCD_1602/coreconsole
LCD_1602/designer
LCD_1602/hdl
LCD_1602/phy_synthesis
LCD_1602/simulation
LCD_1602/smartgen
LCD_1602/stimulus
LCD_1602/synthesis
LCD_1602/viewdraw
LCD_1602
LCD_1602/designer/impl1/designer.log
LCD_1602/designer/impl1/designer_genhdl.log
LCD_1602/designer/impl1/LCD_Driver.ide_des
LCD_1602/designer/impl1/LCD_Top.adb
LCD_1602/designer/impl1/LCD_Top.dtf/verify.log
LCD_1602/designer/impl1/LCD_Top.ide_des
LCD_1602/designer/impl1/LCD_Top.pdb
LCD_1602/designer/impl1/LCD_Top.pdb.depends
LCD_1602/designer/impl1/LCD_Top.tcl
LCD_1602/designer/impl1/LCD_Top_ba.sdf
LCD_1602/designer/impl1/LCD_Top_ba.v
LCD_1602/designer/impl1/LED.ide_des
LCD_1602/designer/impl1/PLL_1M.ide_des
LCD_1602/hdl/Clock_Gen.v
LCD_1602/hdl/LCD_Driver.v
LCD_1602/hdl/LCD_Top.v
LCD_1602/hdl/LED.v
LCD_1602/LCD_1602.prj
LCD_1602/simulation/modelsim.ini
LCD_1602/simulation/modelsim.ini.sav
LCD_1602/smartgen/PLL_1M/PLL_1M.cxf
LCD_1602/smartgen/PLL_1M/PLL_1M.gen
LCD_1602/smartgen/PLL_1M/PLL_1M.log
LCD_1602/smartgen/PLL_1M/PLL_1M.v
LCD_1602/smartgen/PLL_1M_work.ixf
LCD_1602/smartgen/smartgen.aws
LCD_1602/synthesis/.recordref
LCD_1602/synthesis/backup/LCD_Top.srr
LCD_1602/synthesis/LCD_Top.areasrr
LCD_1602/synthesis/LCD_Top.edn
LCD_1602/synthesis/LCD_Top.map
LCD_1602/synthesis/LCD_Top.pdc
LCD_1602/synthesis/LCD_Top.sdf
LCD_1602/synthesis/LCD_Top.so
LCD_1602/synthesis/LCD_Top.srd
LCD_1602/synthesis/LCD_Top.srm
LCD_1602/synthesis/LCD_Top.srr
LCD_1602/synthesis/LCD_Top.srs
LCD_1602/synthesis/LCD_Top.szr
LCD_1602/synthesis/LCD_Top.tlg
LCD_1602/synthesis/LCD_Top_drc.rpt
LCD_1602/synthesis/LCD_Top_sdc.sdc
LCD_1602/synthesis/LCD_Top_syn.prj
LCD_1602/synthesis/run_options.txt
LCD_1602/synthesis/stdout.log
LCD_1602/synthesis/syntmp/LCD_Top.plg
LCD_1602/synthesis/traplog.tlg
LCD_1602/viewdraw/vf/project.lst
LCD_1602/viewdraw/viewdraw.ini
LCD_1602/designer/impl1/LCD_Top.dtf
LCD_1602/designer/impl1/simulation
LCD_1602/designer/impl1
LCD_1602/smartgen/PLL_1M
LCD_1602/synthesis/backup
LCD_1602/synthesis/coreip
LCD_1602/synthesis/syntmp
LCD_1602/viewdraw/sch
LCD_1602/viewdraw/sym
LCD_1602/viewdraw/vf
LCD_1602/viewdraw/wir
LCD_1602/component
LCD_1602/constraint
LCD_1602/coreconsole
LCD_1602/designer
LCD_1602/hdl
LCD_1602/phy_synthesis
LCD_1602/simulation
LCD_1602/smartgen
LCD_1602/stimulus
LCD_1602/synthesis
LCD_1602/viewdraw
LCD_1602
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