文件名称:AlteraSDR-SDRAM
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文件大小:792.51kb
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Altera 官方提供的SDRAM控制器,verilog的-SDRAM controller provided by Altera in Verilog HDL
相关搜索: SDRAM
SDRAM verilog
verilog
sdram controller verilog
verilog SDRAM
Altera SDRAM
Altera
SDRAM FPGA
fpga sdram
sdram vhdl
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下载文件列表
doc/
doc/readme.txt
doc/sdr_sdram.pdf
model/
model/mt48lc8m16a2.v
route/
route/PLL1.v
route/sdr_sdram.csf
route/sdr_sdram.esf
route/sdr_sdram.vqm
simulation/
simulation/modelsim.ini
simulation/readme.txt
simulation/sdr_sdram_tb.v
simulation/work/
simulation/work/altclklock/
simulation/work/altclklock/verilog.psm
simulation/work/altclklock/_primary.dat
simulation/work/altclklock/_primary.vhd
simulation/work/command/
simulation/work/command/verilog.psm
simulation/work/command/_primary.dat
simulation/work/command/_primary.vhd
simulation/work/control_interface/
simulation/work/control_interface/verilog.psm
simulation/work/control_interface/_primary.dat
simulation/work/control_interface/_primary.vhd
simulation/work/mt48lc8m16a2/
simulation/work/mt48lc8m16a2/verilog.psm
simulation/work/mt48lc8m16a2/_primary.dat
simulation/work/mt48lc8m16a2/_primary.vhd
simulation/work/pll1/
simulation/work/pll1/verilog.psm
simulation/work/pll1/_primary.dat
simulation/work/pll1/_primary.vhd
simulation/work/sdr_data_path/
simulation/work/sdr_data_path/verilog.psm
simulation/work/sdr_data_path/_primary.dat
simulation/work/sdr_data_path/_primary.vhd
simulation/work/sdr_sdram/
simulation/work/sdr_sdram/verilog.psm
simulation/work/sdr_sdram/_primary.dat
simulation/work/sdr_sdram/_primary.vhd
simulation/work/sdr_sdram_tb/
simulation/work/sdr_sdram_tb/verilog.psm
simulation/work/sdr_sdram_tb/_primary.dat
simulation/work/sdr_sdram_tb/_primary.vhd
simulation/work/_info
source/
source/altclklock.v
source/Command.v
source/compile_all.v
source/control_interface.v
source/Params.v
source/PLL1.v
source/sdr_data_path.v
source/sdr_sdram.v
synthesis/
synthesis/synplicity/
synthesis/synplicity/sdr_sdram.prj
doc/readme.txt
doc/sdr_sdram.pdf
model/
model/mt48lc8m16a2.v
route/
route/PLL1.v
route/sdr_sdram.csf
route/sdr_sdram.esf
route/sdr_sdram.vqm
simulation/
simulation/modelsim.ini
simulation/readme.txt
simulation/sdr_sdram_tb.v
simulation/work/
simulation/work/altclklock/
simulation/work/altclklock/verilog.psm
simulation/work/altclklock/_primary.dat
simulation/work/altclklock/_primary.vhd
simulation/work/command/
simulation/work/command/verilog.psm
simulation/work/command/_primary.dat
simulation/work/command/_primary.vhd
simulation/work/control_interface/
simulation/work/control_interface/verilog.psm
simulation/work/control_interface/_primary.dat
simulation/work/control_interface/_primary.vhd
simulation/work/mt48lc8m16a2/
simulation/work/mt48lc8m16a2/verilog.psm
simulation/work/mt48lc8m16a2/_primary.dat
simulation/work/mt48lc8m16a2/_primary.vhd
simulation/work/pll1/
simulation/work/pll1/verilog.psm
simulation/work/pll1/_primary.dat
simulation/work/pll1/_primary.vhd
simulation/work/sdr_data_path/
simulation/work/sdr_data_path/verilog.psm
simulation/work/sdr_data_path/_primary.dat
simulation/work/sdr_data_path/_primary.vhd
simulation/work/sdr_sdram/
simulation/work/sdr_sdram/verilog.psm
simulation/work/sdr_sdram/_primary.dat
simulation/work/sdr_sdram/_primary.vhd
simulation/work/sdr_sdram_tb/
simulation/work/sdr_sdram_tb/verilog.psm
simulation/work/sdr_sdram_tb/_primary.dat
simulation/work/sdr_sdram_tb/_primary.vhd
simulation/work/_info
source/
source/altclklock.v
source/Command.v
source/compile_all.v
source/control_interface.v
source/Params.v
source/PLL1.v
source/sdr_data_path.v
source/sdr_sdram.v
synthesis/
synthesis/synplicity/
synthesis/synplicity/sdr_sdram.prj
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