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文件名称:stereo_vision

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    2012-11-16
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Stereo-Vision circuit descr iption, Aug 2002,

Ahmad Darabiha

This design contains four top level circuits: sv_chip0.vhd, sv_chip1.vhd, sv_chip2.vhd and

sv_chip3.vhd each of them built by one Virtex2000E fpga chip. This design is hierarchical and the

sub-circuits can be used as smaller benchmarks.
(系统自动生成,下载前可以参看下载内容)

下载文件列表

stereo_vision/
stereo_vision/basic_type.vhd
stereo_vision/combine_res.vhd
stereo_vision/corr.vhd
stereo_vision/corr_seq.vhd
stereo_vision/fifo.vhd
stereo_vision/find_max.vhd
stereo_vision/fltr_compute_f1.vhd
stereo_vision/fltr_compute_f2.vhd
stereo_vision/fltr_compute_f3.vhd
stereo_vision/fltr_compute_h1.vhd
stereo_vision/fltr_compute_h2.vhd
stereo_vision/fltr_compute_h3.vhd
stereo_vision/fltr_compute_h4.vhd
stereo_vision/h_fltr.vhd
stereo_vision/lp_fltr.vhd
stereo_vision/lp_fltr_v1.vhd
stereo_vision/lp_fltr_v2.vhd
stereo_vision/lp_fltr_v4.vhd
stereo_vision/mult_const_f1_2.edn
stereo_vision/mult_const_f1_3.edn
stereo_vision/mult_const_f1_4.edn
stereo_vision/mult_const_f1_5.edn
stereo_vision/mult_const_f2_2.edn
stereo_vision/mult_const_f2_3.edn
stereo_vision/mult_const_f2_4.edn
stereo_vision/mult_const_f2_5.edn
stereo_vision/mult_const_f3_2.edn
stereo_vision/mult_const_f3_3.edn
stereo_vision/mult_const_f3_4.edn
stereo_vision/mult_const_f3_5.edn
stereo_vision/mult_const_f3_6.edn
stereo_vision/mult_const_f3_7.edn
stereo_vision/mult_const_f3_8.edn
stereo_vision/mult_const_h1_2.edn
stereo_vision/mult_const_h1_3.edn
stereo_vision/mult_const_h1_4.edn
stereo_vision/mult_const_h1_5.edn
stereo_vision/mult_const_h1_6.edn
stereo_vision/mult_const_h1_7.edn
stereo_vision/mult_const_h1_8.edn
stereo_vision/mult_const_h2_2.edn
stereo_vision/mult_const_h2_3.edn
stereo_vision/mult_const_h2_4.edn
stereo_vision/mult_const_h2_5.edn
stereo_vision/mult_const_h3_2.edn
stereo_vision/mult_const_h3_3.edn
stereo_vision/mult_const_h3_4.edn
stereo_vision/mult_const_h3_5.edn
stereo_vision/mult_const_h3_6.edn
stereo_vision/mult_const_h3_7.edn
stereo_vision/mult_const_h3_8.edn
stereo_vision/mult_const_h4_2.edn
stereo_vision/mult_const_h4_3.edn
stereo_vision/mult_const_h4_4.edn
stereo_vision/mult_const_h4_5.edn
stereo_vision/my_div_16.edn
stereo_vision/my_div_16_slow.edn
stereo_vision/my_fifo.edn
stereo_vision/my_fifo_1.edn
stereo_vision/my_fifo_179.edn
stereo_vision/my_fifo_2.edn
stereo_vision/my_fifo_316.edn
stereo_vision/my_fifo_359.edn
stereo_vision/my_fifo_496.edn
stereo_vision/my_fifo_89.edn
stereo_vision/my_fir_f1.edn
stereo_vision/my_fir_f2.edn
stereo_vision/my_fir_f3.edn
stereo_vision/my_fir_h1.edn
stereo_vision/my_fir_h2.edn
stereo_vision/my_fir_h3.edn
stereo_vision/my_fir_h4.edn
stereo_vision/my_mult_8.edn
stereo_vision/my_mult_8_slow.edn
stereo_vision/my_ram.edn
stereo_vision/port_bus_1to0.vhd
stereo_vision/port_bus_1to0_1.vhd
stereo_vision/port_bus_2to1.vhd
stereo_vision/port_bus_2to1_1.vhd
stereo_vision/quadintr_10_20.vhd
stereo_vision/quadintr_5_20.vhd
stereo_vision/README.pdf
stereo_vision/scaler.vhd
stereo_vision/scl_h_fltr.vhd
stereo_vision/scl_v_fltr.vhd
stereo_vision/sh_reg.vhd
stereo_vision/sh_reg_1.vhd
stereo_vision/steer_fltr.vhd
stereo_vision/sv_chip0.vhd
stereo_vision/sv_chip1.vhd
stereo_vision/sv_chip2.vhd
stereo_vision/sv_chip3.vhd
stereo_vision/v_fltr.vhd
stereo_vision/v_fltr_316.vhd
stereo_vision/v_fltr_496.vhd
stereo_vision/wrapper_corr_10.vhd
stereo_vision/wrapper_corr_20.vhd
stereo_vision/wrapper_corr_5_seq.vhd
stereo_vision/wrapper_norm.vhd
stereo_vision/wrapper_norm_corr_10.vhd
stereo_vision/wrapper_norm_corr_20.vhd
stereo_vision/wrapper_norm_corr_5_seq.vhd
stereo_vision/wrapper_norm_seq.vhd
stereo_vision/wrapper_qs_intr_10_20.vhd
stereo_vision/wrapper_qs_intr_5_20.vhd

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