文件名称:FIFO
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- 上传时间:2012-11-16
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文件大小:30.81kb
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it is a verilog code written for FIFO in modelsim simulator and it will synthesize in xinlix ise 8.2i.i have tested it om my kit.[i mae my own kit for spartan2 device].you can use this code in any DSP project in which data entry is required.-it is a verilog code written for FIFO in modelsim simulator and it will synthesize in xinlix ise 8.2i.i have tested it om my kit.[i mae my own kit for spartan2 device].you can use this code in any DSP project in which data entry is required.
相关搜索: fifo modelsim
fifo verilog modelsim
ise fifo
verilog dsp
verilog FIFO
Verilog FIFO code
dsp fifo
FIFO VHDL ISE
FIFO verilog
(系统自动生成,下载前可以参看下载内容)
下载文件列表
FIFO/bench/fifo_tb.v
FIFO/bench/tasks/comp_data.v
FIFO/bench/tasks/Desktop_.ini
FIFO/bench/tasks/initialize_sys.v
FIFO/bench/tasks/mk_infile.v
FIFO/bench/tasks/rd_data.v
FIFO/bench/tasks/reset_sys.v
FIFO/bench/tasks/wrt_data.v
FIFO/rtl/fifo_top.v
FIFO/rtl/ram_blk.v
FIFO/sim/fifo.cr.mti
FIFO/sim/fifo.mpf
FIFO/sim/output_files/ch_data.txt
FIFO/sim/output_files/compare_data.txt
FIFO/sim/output_files/data_rd.txt
FIFO/sim/output_files/Desktop_.ini
FIFO/sim/parameters.v
FIFO/sim/work/Desktop_.ini
FIFO/sim/work/fifo_tb/Desktop_.ini
FIFO/sim/work/fifo_tb/verilog.asm
FIFO/sim/work/fifo_tb/_primary.dat
FIFO/sim/work/fifo_tb/_primary.vhd
FIFO/sim/work/fifo_top/Desktop_.ini
FIFO/sim/work/fifo_top/verilog.asm
FIFO/sim/work/fifo_top/_primary.dat
FIFO/sim/work/fifo_top/_primary.vhd
FIFO/sim/work/ram_32x8/Desktop_.ini
FIFO/sim/work/ram_32x8/verilog.asm
FIFO/sim/work/ram_32x8/_primary.dat
FIFO/sim/work/ram_32x8/_primary.vhd
FIFO/sim/work/ram_blk/verilog.asm
FIFO/sim/work/ram_blk/_primary.dat
FIFO/sim/work/ram_blk/_primary.vhd
FIFO/sim/work/_info
FIFO/sim/work/fifo_tb
FIFO/sim/work/fifo_top
FIFO/sim/work/ram_32x8
FIFO/sim/work/ram_blk
FIFO/bench/tasks
FIFO/sim/output_files
FIFO/sim/work
FIFO/bench
FIFO/rtl
FIFO/sim
FIFO
FIFO/bench/tasks/comp_data.v
FIFO/bench/tasks/Desktop_.ini
FIFO/bench/tasks/initialize_sys.v
FIFO/bench/tasks/mk_infile.v
FIFO/bench/tasks/rd_data.v
FIFO/bench/tasks/reset_sys.v
FIFO/bench/tasks/wrt_data.v
FIFO/rtl/fifo_top.v
FIFO/rtl/ram_blk.v
FIFO/sim/fifo.cr.mti
FIFO/sim/fifo.mpf
FIFO/sim/output_files/ch_data.txt
FIFO/sim/output_files/compare_data.txt
FIFO/sim/output_files/data_rd.txt
FIFO/sim/output_files/Desktop_.ini
FIFO/sim/parameters.v
FIFO/sim/work/Desktop_.ini
FIFO/sim/work/fifo_tb/Desktop_.ini
FIFO/sim/work/fifo_tb/verilog.asm
FIFO/sim/work/fifo_tb/_primary.dat
FIFO/sim/work/fifo_tb/_primary.vhd
FIFO/sim/work/fifo_top/Desktop_.ini
FIFO/sim/work/fifo_top/verilog.asm
FIFO/sim/work/fifo_top/_primary.dat
FIFO/sim/work/fifo_top/_primary.vhd
FIFO/sim/work/ram_32x8/Desktop_.ini
FIFO/sim/work/ram_32x8/verilog.asm
FIFO/sim/work/ram_32x8/_primary.dat
FIFO/sim/work/ram_32x8/_primary.vhd
FIFO/sim/work/ram_blk/verilog.asm
FIFO/sim/work/ram_blk/_primary.dat
FIFO/sim/work/ram_blk/_primary.vhd
FIFO/sim/work/_info
FIFO/sim/work/fifo_tb
FIFO/sim/work/fifo_top
FIFO/sim/work/ram_32x8
FIFO/sim/work/ram_blk
FIFO/bench/tasks
FIFO/sim/output_files
FIFO/sim/work
FIFO/bench
FIFO/rtl
FIFO/sim
FIFO
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