文件名称:UART_for_FPGArar
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- 上传时间:2012-11-16
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文件大小:5.45kb
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it is a verilog code written for MELAY state machine based UART and it wll synthesize in xinlix ise 8.2i.i have tested it om my kit.[i mae my own kit for spartan2 device]-it is a verilog code written for MELAY state machine based UART and it wll synthesize in xinlix ise 8.2i.i have tested it om my kit.[i mae my own kit for spartan2 device]
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下载文件列表
rtl/Desktop_.ini
rtl/uart_top.v
rtl/uar_sm.v
rtl/uar_top.v
rtl/uat_sm.v
rtl/uat_top.v
rtl
rtl/uart_top.v
rtl/uar_sm.v
rtl/uar_top.v
rtl/uat_sm.v
rtl/uat_top.v
rtl
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