文件名称:uart
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uart协议、实现、验证,基于wishbone协议,工业标准为16550A-UART protocol, implementation, verification, based on the Wishbone protocol, the industry standard for the 16550A
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下载文件列表
bench/
bench/verilog/
bench/verilog/readme.txt
bench/verilog/test_cases/
bench/verilog/test_cases/uart_int.v
bench/verilog/uart_device.v
bench/verilog/uart_device_utilities.v
bench/verilog/uart_log.v
bench/verilog/uart_test.v
bench/verilog/uart_testbench.v
bench/verilog/uart_testbench_defines.v
bench/verilog/uart_testbench_utilities.v
bench/verilog/uart_wb_utilities.v
bench/verilog/vapi.log
bench/verilog/wb_mast.v
bench/verilog/wb_master_model.v
bench/verilog/wb_model_defines.v
bench/vhdl/
bench/vhdl/.keepme
doc/
doc/CHANGES.txt
doc/UART_spec.pdf
fv/
fv/.keepme
lint/
lint/bin/
lint/bin/.keepme
lint/log/
lint/log/.keepme
lint/out/
lint/out/.keepme
lint/run/
lint/run/.keepme
rtl/
rtl/verilog/
rtl/verilog/raminfr.v
rtl/verilog/timescale.v
rtl/verilog/uart_debug_if.v
rtl/verilog/uart_defines.v
rtl/verilog/uart_receiver.v
rtl/verilog/uart_regs.v
rtl/verilog/uart_rfifo.v
rtl/verilog/uart_sync_flops.v
rtl/verilog/uart_tfifo.v
rtl/verilog/uart_top.v
rtl/verilog/uart_transmitter.v
rtl/verilog/uart_wb.v
rtl/verilog-backup/
rtl/verilog-backup/timescale.v
rtl/verilog-backup/uart_defines.v
rtl/verilog-backup/uart_fifo.v
rtl/verilog-backup/uart_receiver.v
rtl/verilog-backup/uart_regs.v
rtl/verilog-backup/uart_top.v
rtl/verilog-backup/uart_transmitter.v
rtl/verilog-backup/uart_wb.v
rtl/vhdl/
rtl/vhdl/.keepme
sim/
sim/gate_sim/
sim/gate_sim/bin/
sim/gate_sim/bin/.keepme
sim/gate_sim/log/
sim/gate_sim/log/.keepme
sim/gate_sim/out/
sim/gate_sim/out/.keepme
sim/gate_sim/run/
sim/gate_sim/run/.keepme
sim/gate_sim/src/
sim/gate_sim/src/.keepme
sim/rtl_sim/
sim/rtl_sim/bin/
sim/rtl_sim/bin/nc.scr
sim/rtl_sim/bin/sim.tcl
sim/rtl_sim/log/
sim/rtl_sim/log/.keepme
sim/rtl_sim/log/uart_interrupts_report.log
sim/rtl_sim/log/uart_interrupts_verbose.log
sim/rtl_sim/out/
sim/rtl_sim/out/.keepme
sim/rtl_sim/run/
sim/rtl_sim/run/run_signalscan
sim/rtl_sim/run/run_sim
sim/rtl_sim/run/run_sim.scr
sim/rtl_sim/src/
sim/rtl_sim/src/.keepme
syn/
syn/bin/
syn/bin/.keepme
syn/log/
syn/log/.keepme
syn/out/
syn/out/.keepme
syn/run/
syn/run/.keepme
syn/src/
syn/src/.keepme
bench/verilog/
bench/verilog/readme.txt
bench/verilog/test_cases/
bench/verilog/test_cases/uart_int.v
bench/verilog/uart_device.v
bench/verilog/uart_device_utilities.v
bench/verilog/uart_log.v
bench/verilog/uart_test.v
bench/verilog/uart_testbench.v
bench/verilog/uart_testbench_defines.v
bench/verilog/uart_testbench_utilities.v
bench/verilog/uart_wb_utilities.v
bench/verilog/vapi.log
bench/verilog/wb_mast.v
bench/verilog/wb_master_model.v
bench/verilog/wb_model_defines.v
bench/vhdl/
bench/vhdl/.keepme
doc/
doc/CHANGES.txt
doc/UART_spec.pdf
fv/
fv/.keepme
lint/
lint/bin/
lint/bin/.keepme
lint/log/
lint/log/.keepme
lint/out/
lint/out/.keepme
lint/run/
lint/run/.keepme
rtl/
rtl/verilog/
rtl/verilog/raminfr.v
rtl/verilog/timescale.v
rtl/verilog/uart_debug_if.v
rtl/verilog/uart_defines.v
rtl/verilog/uart_receiver.v
rtl/verilog/uart_regs.v
rtl/verilog/uart_rfifo.v
rtl/verilog/uart_sync_flops.v
rtl/verilog/uart_tfifo.v
rtl/verilog/uart_top.v
rtl/verilog/uart_transmitter.v
rtl/verilog/uart_wb.v
rtl/verilog-backup/
rtl/verilog-backup/timescale.v
rtl/verilog-backup/uart_defines.v
rtl/verilog-backup/uart_fifo.v
rtl/verilog-backup/uart_receiver.v
rtl/verilog-backup/uart_regs.v
rtl/verilog-backup/uart_top.v
rtl/verilog-backup/uart_transmitter.v
rtl/verilog-backup/uart_wb.v
rtl/vhdl/
rtl/vhdl/.keepme
sim/
sim/gate_sim/
sim/gate_sim/bin/
sim/gate_sim/bin/.keepme
sim/gate_sim/log/
sim/gate_sim/log/.keepme
sim/gate_sim/out/
sim/gate_sim/out/.keepme
sim/gate_sim/run/
sim/gate_sim/run/.keepme
sim/gate_sim/src/
sim/gate_sim/src/.keepme
sim/rtl_sim/
sim/rtl_sim/bin/
sim/rtl_sim/bin/nc.scr
sim/rtl_sim/bin/sim.tcl
sim/rtl_sim/log/
sim/rtl_sim/log/.keepme
sim/rtl_sim/log/uart_interrupts_report.log
sim/rtl_sim/log/uart_interrupts_verbose.log
sim/rtl_sim/out/
sim/rtl_sim/out/.keepme
sim/rtl_sim/run/
sim/rtl_sim/run/run_signalscan
sim/rtl_sim/run/run_sim
sim/rtl_sim/run/run_sim.scr
sim/rtl_sim/src/
sim/rtl_sim/src/.keepme
syn/
syn/bin/
syn/bin/.keepme
syn/log/
syn/log/.keepme
syn/out/
syn/out/.keepme
syn/run/
syn/run/.keepme
syn/src/
syn/src/.keepme
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