文件名称:project1_report1
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The purpose of this project is to explore the issues and implementation of a multiple instruction stream, single data stream processor. We are running two instruction streams on two CPUs which share an address space. The processors share a second level cache, and maintain coherence at the L1 cache with a write-invalidate policy. The L2 cache is two-way set associative, with a block size of 8 words, and a total capacity of 512 words.
相关搜索: vhdl cache
cache vhdl
coherence
cache
Space-Time-Codes-and-MIMO-Systems_book
Multiple level Cache
cache coherence
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project1_report1.doc
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