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文件名称:VHDLprogram

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  • 上传时间:
    2012-11-16
  • 文件大小:
    1.72mb
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    别用迅雷下载,失败请重下,重下不扣分!

介绍说明--下载内容来自于网络,使用问题请自行百度

含有各类寄存器,AD和DA转换器,各种算法,有限状态机,还些许组合逻辑电路设计代码-Containing various types of registers, AD and DA converters, a variety of algorithms, finite state machine, but also some combinational logic circuit design code
(系统自动生成,下载前可以参看下载内容)

下载文件列表

RadarSim/UserInterface.vhd
RadarSim/PackForSim.vhd
RadarSim/RadarSimA.vhd
RadarSim/TargetGen.vhd
RadarSim/ucr_radarsim.ucf
RadarSim/RadarSim.ise
RadarSim/RadarSim.ise_ISE_Backup
RadarSim/RadarSimA_summary.html
RadarSim/RadarSim.ntrc_log
RadarSim/RadarSimA.ut
RadarSim/RadarSimA_usage.xml
RadarSim/test.vhd
test_RAM/test_RAM.ise
test_RAM/test_RAM.ise_ISE_Backup
test_RAM/testram_summary.html
test_RAM/testram.vhd
test_RAM/test_RAM.ntrc_log
test_RAM/testram.ut
test_RAM/testram_usage.xml
test_RAM/test_RAM.ucf
test_RAM/test_RAM_E.ucf
test_RAM/vga_16.vhd
test_ROM/test_ROM.ise
test_ROM/_cg/rom256x16.mif
test_ROM/rom256x16.coe
test_ROM/TESTROM_summary.html
test_ROM/rom256x16.mif
test_ROM/rom256x16.edn
test_ROM/rom256x16.vhd
test_ROM/rom256x16.vho
test_ROM/rom256x16.v
test_ROM/rom256x16.xco
test_ROM/rom256x16.veo
test_ROM/rom256x16.asy
test_ROM/test.vhd
test_ROM/rom256x16.sym
test_ROM/rom256x16_flist.txt
test_ROM/templates/coregen.xml
test_ROM/testrom.vhd
test_ROM/test_ROM.ntrc_log
test_ROM/TESTROM.ut
test_ROM/TESTROM_last_par.ncd
test_ROM/test_ROM.ucf
test_ROM/test_rom1.xco
test_ROM/test_ROM_E.ucf
test_ROM/vga_16.vhd
test_ROM/test_ROM.ise_ISE_Backup
VHDL例程/AD和DA转换器/16bit数模转换器.vhd
VHDL例程/AD和DA转换器/16bit模数转换器.vhd
VHDL例程/AD和DA转换器/8-bit Unipolar Successive Approximation ADC.vhd
VHDL例程/AD和DA转换器/8bit模数和数模转换器.vhd
VHDL例程/AD和DA转换器/基本模拟包定义.vhd
VHDL例程/AD和DA转换器/带RAM和控制处理器的数字延时单元.vhd
VHDL例程/各种算法/n位加法器.vhd
VHDL例程/各种算法/八位无符号乘法器.vhd
VHDL例程/各种算法/加法器源程序.vhd
VHDL例程/各种算法/布斯乘法器.vhd
VHDL例程/存储器/FIFO存储器.vhd
VHDL例程/存储器/RAM_16W8B.vhd
VHDL例程/存储器/RAM_256W8B.vhd
VHDL例程/存储器/ROM_based_waveform.vhd
VHDL例程/寄存器/ttl374.vhd
VHDL例程/寄存器/四D触发器74175.vhd
VHDL例程/寄存器/带load_clr等功能的寄存器.vhd
VHDL例程/寄存器/简单的12位寄存器.vhd
VHDL例程/寄存器/简单的锁存器.vhd
VHDL例程/有限状态机/带同步复位的状态机.vhd
VHDL例程/有限状态机/带莫尔_米勒输出的状态机.vhd
VHDL例程/有限状态机/简单的状态机.vhd
VHDL例程/有限状态机/米勒型状态机.vhd
VHDL例程/有限状态机/莫尔型状态机.vhd
VHDL例程/移位寄存器设计/R74194.vhd
VHDL例程/移位寄存器设计/Shift_8bit.vhd
VHDL例程/移位寄存器设计/移位寄存器_8bit.vhd
VHDL例程/移位寄存器设计/移位寄存器_TTL164.vhd
VHDL例程/移位寄存器设计/通用寄存器.vhd
VHDL例程/简单数字系统设计/CNT8.VHD
VHDL例程/简单数字系统设计/EDA6波形发生器.doc
VHDL例程/简单数字系统设计/EDA6波形发生器.vhd
VHDL例程/简单数字系统设计/EDA7彩灯及键盘抖动的演示.doc
VHDL例程/简单数字系统设计/EDA7彩灯及键盘抖动的演示.vhd
VHDL例程/简单数字系统设计/VGA.VHD
VHDL例程/简单数字系统设计/一个游戏程序.vhd
VHDL例程/简单数字系统设计/一个简单的UART.vhd
VHDL例程/简单数字系统设计/可控脉冲发生器.VHD
VHDL例程/简单数字系统设计/序列检测器.VHD
VHDL例程/简单数字系统设计/正负脉宽数控调制信号发生器.VHD
VHDL例程/简单数字系统设计/步进电机控制器.vhd
VHDL例程/简单数字系统设计/波形发生器.vhd
VHDL例程/简单数字系统设计/直流电机控制器.vhd
VHDL例程/简单数字系统设计/象棋钟.vhd
VHDL例程/组合逻辑电路设计/4bitBCD加法.VHD
VHDL例程/组合逻辑电路设计/4选1.vhd
VHDL例程/组合逻辑电路设计/74138.vhd
VHDL例程/组合逻辑电路设计/7人表决器VOTE7.VHD
VHDL例程/组合逻辑电路设计/8位总线收发器_74245.vhd
VHDL例程/组合逻辑电路设计/8位相等比较器.vhd
VHDL例程/组合逻辑电路设计/LED七段译码.vhd
VHDL例程/组合逻辑电路设计/LS160.VHD
VHDL例程/组合逻辑电路设计/三人表决器.vhd
VHDL例程/组合逻辑电路设计/三态总线.vhd
VHDL例程/组合逻辑电路设计/与非门_HCT00.vhd
VHDL例程/组合逻辑电路设计/优先级编码器.vhd
VHDL例程/组合逻辑电路设计/伪随机数产生器.vhd
VHDL例程/组合逻辑电路设计/双2-4译码器_74139.vhd
VHDL例程/组合逻辑电路设计/双向总线.vhd
VHDL例程/组合逻辑电路设计/地址译码器.vhd
VHDL例程/组合逻辑电路设计/多路选择器16_4.vhd
VHDL例程/组合逻辑电路设计/格雷码变换器.VHD
VHDL例程/组合逻辑电路设计/比较器_4bit.vhd
VHDL例程/组合逻辑电路设计/汉明纠错码编码器_译码器.vhd
VHDL例程/计数器设计/Binary_UpCounter.vhd
VHDL例程/计数器设计/Counter_using_Multiple_Wait.vhd
VHDL例程/计数器设计/Mod_16Counter.vhd
VHDL例程/计数器设计/nBit_Synchronous_Counter.vhd
VHDL例程/计数器设计/可变步长加减计数器.VHD
VHDL例程/计数器设计/各种功能的计数器.vhd
adder/adder.vhd
adder/adder.ise
adder/adder_cs.ucf
adder/adder.ise_ISE_Backup
adder/adder_summary.html
adder/adder.ntrc_log
adder/adder_prev_built.ngd
adder/adder_cs.cel
adder/adder.ut
adder_cs/adder_CS_summary.html
adder_cs/adder_cs.ise
adder_cs/iscas.vhd
adder_cs/adder_cs.ise_ISE_Backup
adder_cs/adder_CS.ut
adder_cs/adder_cs.ucf
adder_cs/adder_CS.vhd
adder_cs/adder_cs.ntrc_log
adder_cs/test.vhd
adder_cs/test_PK.vhd
count/count.ise
count/__ISE_repository_count.ise_.lock
count/count.ise_ISE_Backup
count/counter_summary.html
count/core_counnt.xco
count/core_counnt.edn
count/core_counnt.vhd
count/core_counnt.vho
count/core_counnt.v
count/core_counnt.veo
count/core_counnt.asy
count/core_counnt.sym
count/core_count.xco
count/core_counnt_flist.txt
count/templates/coregen.xml
count/count.ntrc_log
count/counter.ucf
count/counter.vhd
count/counter.ut
count/test.xco
count/vga_16.vhd
count_core/count_core.ise
count_core/count_top_summary.html
count_core/counter.v
count_core/counter.edn
count_core/counter.vhd
count_core/counter.vho
count_core/counter.xco
count_core/counter.veo
count_core/counter.asy
count_core/counter.sym
count_core/counter_flist.txt
count_core/count_core.ntrc_log
count_core/count_top.ut
count_core/count_top.vhd
count_core/HEX2LED_4.vhd
count_core/vga_16.vhd
count_core/templates/coregen.xml
count_core/count_core.ise_ISE_Backup
counter/__ISE_repository_counter.ise_.lock
counter/counter.ise
counter/counter.ise_ISE_Backup
counter/counter.vhd
counter/count_sim.tbw
counter/counter.ntrc_log
counter/count_top.ut
counter/count_top.vhd
counter/count_top_summary.html
counter/HEX2LED_4.vhd
counter/vga_16.vhd
counter/work/_info
counter/work/count/behavioral.asm
counter/work/count/behavioral.dat
counter/work/count/_primary.dat
counter/work/counter/behavioral.asm
counter/work/counter/behavioral.dat
counter/work/counter/_primary.dat
counter/work/counter_cfg/_primary.dat
counter/work/counter_cfg/_vhdl.asm
counter/

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