文件名称:EP1C6Q240-8REG_WR
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- 上传时间:2012-11-16
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文件大小:517.17kb
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altera公司的FPGA的一些开发用的VHDL的源代码用于学习-altera INC. develop fpga vhdl source for study and research
(系统自动生成,下载前可以参看下载内容)
下载文件列表
reg_wr/write.vhd
reg_wr/test.qws
reg_wr/test.bdf
reg_wr/test.done
reg_wr/read.bsf
reg_wr/read.vhd
reg_wr/ff_waveforms.html
reg_wr/ff_wave0.jpg
reg_wr/ff.vhd
reg_wr/ff.cmp
reg_wr/ff.bsf
reg_wr/Rint.bsf
reg_wr/Rint.vhd
reg_wr/int.bsf
reg_wr/a.v
reg_wr/a.vhd
reg_wr/aa.v
reg_wr/test.map.summary
reg_wr/test.map.rpt
reg_wr/test.flow.rpt
reg_wr/test.sim.rpt
reg_wr/test.tan.rpt
reg_wr/test.sof
reg_wr/test.pof
reg_wr/test.asm.rpt
reg_wr/test.pin
reg_wr/test.fit.summary
reg_wr/test.fit.smsg
reg_wr/test.fit.rpt
reg_wr/Waveform1.vwf
reg_wr/interrupt.vhd
reg_wr/test.vhd
reg_wr/74138_0.vhd
reg_wr/test.tan.summary
reg_wr/test.vwf
reg_wr/interrupt.bsf
reg_wr/test.dpf
reg_wr/test.tcl
reg_wr/tTRI.vhd
reg_wr/tTRI.cmp
reg_wr/tTRI.bsf
reg_wr/test.cdf
reg_wr/test.qpf
reg_wr/pllll_waveforms.html
reg_wr/pllll_wave0.jpg
reg_wr/pllll.ppf
reg_wr/pllll.vhd
reg_wr/pllll.cmp
reg_wr/pllll.bsf
reg_wr/cmp_state.ini
reg_wr/bt.vhd
reg_wr/bt.cmp
reg_wr/bt.bsf
reg_wr/sim.cfg
reg_wr/test_assignment_defaults.qdf
reg_wr/test.qsf.bak
reg_wr/test.qsf
reg_wr/test.map.eqn
reg_wr/test.fit.eqn
reg_wr/test.fld
reg_wr/int.vhd.bak
reg_wr/int.vhd
reg_wr/_desktop.ini
reg_wr/db/test.cmp.hdb
reg_wr/db/wed.zsf
reg_wr/db/test.tan.qmsg
reg_wr/db/test.cmp.rdb
reg_wr/db/test.syn_hier_info
reg_wr/db/test.signalprobe.cdb
reg_wr/db/test.cmp.tdb
reg_wr/db/test.(0).cnf.cdb
reg_wr/db/test.cmp0.ddb
reg_wr/db/test.(0).cnf.hdb
reg_wr/db/test.cmp.cdb
reg_wr/db/test.sld_design_entry.sci
reg_wr/db/test.eco.cdb
reg_wr/db/test_cmp.qrpt
reg_wr/db/test.sim.qmsg
reg_wr/db/test.eds_overflow
reg_wr/db/test.sim.hdb
reg_wr/db/test.sim.vwf
reg_wr/db/test.sim.qrpt
reg_wr/db/test.sim.rdb
reg_wr/db/test_sim.qrpt
reg_wr/db/test.db_info
reg_wr/db/test.cmp.qrpt
reg_wr/db/test.cbx.xml
reg_wr/db/test.hif
reg_wr/db/test.(1).cnf.cdb
reg_wr/db/test.(1).cnf.hdb
reg_wr/db/test.(2).cnf.cdb
reg_wr/db/test.(2).cnf.hdb
reg_wr/db/test.(4).cnf.cdb
reg_wr/db/test.(4).cnf.hdb
reg_wr/db/test.(5).cnf.cdb
reg_wr/db/test.(5).cnf.hdb
reg_wr/db/test.hier_info
reg_wr/db/test.psp
reg_wr/db/test.dbp
reg_wr/db/_desktop.ini
reg_wr/db/test.map.qmsg
reg_wr/db/test.(3).cnf.cdb
reg_wr/db/test.(3).cnf.hdb
reg_wr/db/test.rtlv_sg.cdb
reg_wr/db/test.rtlv.hdb
reg_wr/db/test.rtlv_sg_swap.cdb
reg_wr/db/test.pre_map.hdb
reg_wr/db/test.pre_map.cdb
reg_wr/db/test.smp_dump.txt
reg_wr/db/test.sgdiff.cdb
reg_wr/db/test.sgdiff.hdb
reg_wr/db/test.sld_design_entry_dsc.sci
reg_wr/db/test.map.cdb
reg_wr/db/test.map.hdb
reg_wr/db/test.fit.qmsg
reg_wr/db/test.asm.qmsg
reg_wr/db
reg_wr
reg_wr/test.qws
reg_wr/test.bdf
reg_wr/test.done
reg_wr/read.bsf
reg_wr/read.vhd
reg_wr/ff_waveforms.html
reg_wr/ff_wave0.jpg
reg_wr/ff.vhd
reg_wr/ff.cmp
reg_wr/ff.bsf
reg_wr/Rint.bsf
reg_wr/Rint.vhd
reg_wr/int.bsf
reg_wr/a.v
reg_wr/a.vhd
reg_wr/aa.v
reg_wr/test.map.summary
reg_wr/test.map.rpt
reg_wr/test.flow.rpt
reg_wr/test.sim.rpt
reg_wr/test.tan.rpt
reg_wr/test.sof
reg_wr/test.pof
reg_wr/test.asm.rpt
reg_wr/test.pin
reg_wr/test.fit.summary
reg_wr/test.fit.smsg
reg_wr/test.fit.rpt
reg_wr/Waveform1.vwf
reg_wr/interrupt.vhd
reg_wr/test.vhd
reg_wr/74138_0.vhd
reg_wr/test.tan.summary
reg_wr/test.vwf
reg_wr/interrupt.bsf
reg_wr/test.dpf
reg_wr/test.tcl
reg_wr/tTRI.vhd
reg_wr/tTRI.cmp
reg_wr/tTRI.bsf
reg_wr/test.cdf
reg_wr/test.qpf
reg_wr/pllll_waveforms.html
reg_wr/pllll_wave0.jpg
reg_wr/pllll.ppf
reg_wr/pllll.vhd
reg_wr/pllll.cmp
reg_wr/pllll.bsf
reg_wr/cmp_state.ini
reg_wr/bt.vhd
reg_wr/bt.cmp
reg_wr/bt.bsf
reg_wr/sim.cfg
reg_wr/test_assignment_defaults.qdf
reg_wr/test.qsf.bak
reg_wr/test.qsf
reg_wr/test.map.eqn
reg_wr/test.fit.eqn
reg_wr/test.fld
reg_wr/int.vhd.bak
reg_wr/int.vhd
reg_wr/_desktop.ini
reg_wr/db/test.cmp.hdb
reg_wr/db/wed.zsf
reg_wr/db/test.tan.qmsg
reg_wr/db/test.cmp.rdb
reg_wr/db/test.syn_hier_info
reg_wr/db/test.signalprobe.cdb
reg_wr/db/test.cmp.tdb
reg_wr/db/test.(0).cnf.cdb
reg_wr/db/test.cmp0.ddb
reg_wr/db/test.(0).cnf.hdb
reg_wr/db/test.cmp.cdb
reg_wr/db/test.sld_design_entry.sci
reg_wr/db/test.eco.cdb
reg_wr/db/test_cmp.qrpt
reg_wr/db/test.sim.qmsg
reg_wr/db/test.eds_overflow
reg_wr/db/test.sim.hdb
reg_wr/db/test.sim.vwf
reg_wr/db/test.sim.qrpt
reg_wr/db/test.sim.rdb
reg_wr/db/test_sim.qrpt
reg_wr/db/test.db_info
reg_wr/db/test.cmp.qrpt
reg_wr/db/test.cbx.xml
reg_wr/db/test.hif
reg_wr/db/test.(1).cnf.cdb
reg_wr/db/test.(1).cnf.hdb
reg_wr/db/test.(2).cnf.cdb
reg_wr/db/test.(2).cnf.hdb
reg_wr/db/test.(4).cnf.cdb
reg_wr/db/test.(4).cnf.hdb
reg_wr/db/test.(5).cnf.cdb
reg_wr/db/test.(5).cnf.hdb
reg_wr/db/test.hier_info
reg_wr/db/test.psp
reg_wr/db/test.dbp
reg_wr/db/_desktop.ini
reg_wr/db/test.map.qmsg
reg_wr/db/test.(3).cnf.cdb
reg_wr/db/test.(3).cnf.hdb
reg_wr/db/test.rtlv_sg.cdb
reg_wr/db/test.rtlv.hdb
reg_wr/db/test.rtlv_sg_swap.cdb
reg_wr/db/test.pre_map.hdb
reg_wr/db/test.pre_map.cdb
reg_wr/db/test.smp_dump.txt
reg_wr/db/test.sgdiff.cdb
reg_wr/db/test.sgdiff.hdb
reg_wr/db/test.sld_design_entry_dsc.sci
reg_wr/db/test.map.cdb
reg_wr/db/test.map.hdb
reg_wr/db/test.fit.qmsg
reg_wr/db/test.asm.qmsg
reg_wr/db
reg_wr
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