本文研究了SMBus

规范，介绍了典型的基于片上系统（SoC）设计的知识产权核（IP）实现，采用自顶向下

(Top-down)的集成电路设计方法完成了设计，并架构了基于总线功能模型(BFM)的验证平台

完成功能仿真，顺利完成了逻辑综合和时序仿真。FPGA 验证和投片后测试均表明设计具有

良好的性能。-This paper studies the SMBus specification, based on the introduction of the typical system-on-chip (SoC) intellectual property core design (IP) implementation, using top-down (Top-down) of the integrated circuit design methods achieve a design and architecture based on the total Line functional model (BFM) achieve functional verification platform for simulation, successfully completed a logic synthesis and timing simulation. FPGA silicon validation and post-tests show that the design has good performance.