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文件名称:core8051_lcd1602

  • 所属分类：
    Other systems
  • 标签属性：
    [VHDL] [源码]
  • 上传时间：
    2012-11-16
  • 文件大小：
    14mb
  • 已下载：
    1次
  • 提 供 者：
    冰***
  • 相关连接：
    无
  • 下载说明：
    别用迅雷下载，失败请重下，重下不扣分！
修正介绍说明

介绍说明－－下载内容来自于网络，使用问题请自行百度

基于Fusion系列AFS600的FPGA的51核，在板子上试过，可以对51核写1602的显示程序，就可以显示了，也可以写其他的51程序。-AFS600-based Fusion Series of FPGA 51 nuclear, tried on the board, you can write 1602 on 51 of the display of the nuclear program, we can show that we can process other 51.
相关搜索： actel core8051 16 core8051 16 Fusion AFS600 actel lcd_driver AFS600 LCD 8051co

(系统自动生成,下载前可以参看下载内容)

下载文件列表

core8051_lcd1602/constraint/USER_CORE8051.pdc
core8051_lcd1602/core8051.prj
core8051_lcd1602/core8051.prj.convert.8.0.bak
core8051_lcd1602/core8051.prj.convert.8.1.bak
core8051_lcd1602/designer/impl1/ada02172-1.tmp
core8051_lcd1602/designer/impl1/ada02172-3.tmp
core8051_lcd1602/designer/impl1/ada02392-3.tmp
core8051_lcd1602/designer/impl1/ada02392-5.tmp
core8051_lcd1602/designer/impl1/designer.log
core8051_lcd1602/designer/impl1/designer_genhdl.log
core8051_lcd1602/designer/impl1/simulation/postlayout/@u@s@e@r_@c@o@r@e8051/verilog.psm
core8051_lcd1602/designer/impl1/simulation/postlayout/@u@s@e@r_@c@o@r@e8051/_primary.dat
core8051_lcd1602/designer/impl1/simulation/postlayout/@u@s@e@r_@c@o@r@e8051/_primary.dbs
core8051_lcd1602/designer/impl1/simulation/postlayout/@u@s@e@r_@c@o@r@e8051/_primary.vhd
core8051_lcd1602/designer/impl1/simulation/postlayout/stimulus/verilog.psm
core8051_lcd1602/designer/impl1/simulation/postlayout/stimulus/_primary.dat
core8051_lcd1602/designer/impl1/simulation/postlayout/stimulus/_primary.dbs
core8051_lcd1602/designer/impl1/simulation/postlayout/stimulus/_primary.vhd
core8051_lcd1602/designer/impl1/simulation/postlayout/tb_clock_minmax/verilog.psm
core8051_lcd1602/designer/impl1/simulation/postlayout/tb_clock_minmax/_primary.dat
core8051_lcd1602/designer/impl1/simulation/postlayout/tb_clock_minmax/_primary.dbs
core8051_lcd1602/designer/impl1/simulation/postlayout/tb_clock_minmax/_primary.vhd
core8051_lcd1602/designer/impl1/simulation/postlayout/_info
core8051_lcd1602/designer/impl1/USER_CORE8051.adb
core8051_lcd1602/designer/impl1/USER_CORE8051.dtf/verify.log
core8051_lcd1602/designer/impl1/USER_CORE8051.ide_des
core8051_lcd1602/designer/impl1/USER_CORE8051.pdb
core8051_lcd1602/designer/impl1/USER_CORE8051.pdb.depends
core8051_lcd1602/designer/impl1/USER_CORE8051.tcl
core8051_lcd1602/designer/impl1/USER_CORE8051_ba.sdf
core8051_lcd1602/designer/impl1/USER_CORE8051_ba.v
core8051_lcd1602/designer/impl1/USER_CORE8051_fp/$$FlashPro_FPBBALTLPT1.L$$
core8051_lcd1602/designer/impl1/USER_CORE8051_fp/projectData/USER_CORE8051.pdb
core8051_lcd1602/designer/impl1/USER_CORE8051_fp/USER_CORE8051.log
core8051_lcd1602/designer/impl1/USER_CORE8051_fp_1/$$FlashPro_FPBBALTLPT1.L$$
core8051_lcd1602/designer/impl1/USER_CORE8051_fp_1/projectData/USER_CORE8051.pdb
core8051_lcd1602/designer/impl1/USER_CORE8051_fp_1/USER_CORE8051.log
core8051_lcd1602/designer/impl1/USER_CORE8051_fp_1/USER_CORE8051.pro
core8051_lcd1602/hdl/core8051_oci0_withoutio_pa3.v
core8051_lcd1602/hdl/Core8051_ROM_Ctr.v
core8051_lcd1602/hdl/user_core8051.v
core8051_lcd1602/simulation/data_store_LCD1602-4BIT.hex
core8051_lcd1602/simulation/data_store_WL030.hex
core8051_lcd1602/simulation/data_store_zhousfe.hex
core8051_lcd1602/simulation/flashmem.mem
core8051_lcd1602/simulation/flashmem_test.hex
core8051_lcd1602/simulation/meminit.dat
core8051_lcd1602/simulation/modelsim.ini
core8051_lcd1602/simulation/modelsim.ini.sav
core8051_lcd1602/simulation/modelsim.log
core8051_lcd1602/simulation/postsynth/@c@o@r@e8051/verilog.psm
core8051_lcd1602/simulation/postsynth/@c@o@r@e8051/_primary.dat
core8051_lcd1602/simulation/postsynth/@c@o@r@e8051/_primary.dbs
core8051_lcd1602/simulation/postsynth/@c@o@r@e8051/_primary.vhd
core8051_lcd1602/simulation/postsynth/@core8051_@r@o@m_@ctr/verilog.psm
core8051_lcd1602/simulation/postsynth/@core8051_@r@o@m_@ctr/_primary.dat
core8051_lcd1602/simulation/postsynth/@core8051_@r@o@m_@ctr/_primary.dbs
core8051_lcd1602/simulation/postsynth/@core8051_@r@o@m_@ctr/_primary.vhd
core8051_lcd1602/simulation/postsynth/@r@a@m256@x8/verilog.psm
core8051_lcd1602/simulation/postsynth/@r@a@m256@x8/_primary.dat
core8051_lcd1602/simulation/postsynth/@r@a@m256@x8/_primary.dbs
core8051_lcd1602/simulation/postsynth/@r@a@m256@x8/_primary.vhd
core8051_lcd1602/simulation/postsynth/@u@s@e@r_@c@o@r@e8051/verilog.psm
core8051_lcd1602/simulation/postsynth/@u@s@e@r_@c@o@r@e8051/_primary.dat
core8051_lcd1602/simulation/postsynth/@u@s@e@r_@c@o@r@e8051/_primary.dbs
core8051_lcd1602/simulation/postsynth/@u@s@e@r_@c@o@r@e8051/_primary.vhd
core8051_lcd1602/simulation/postsynth/@x@y@x@x0001/verilog.psm
core8051_lcd1602/simulation/postsynth/@x@y@x@x0001/_primary.dat
core8051_lcd1602/simulation/postsynth/@x@y@x@x0001/_primary.dbs
core8051_lcd1602/simulation/postsynth/@x@y@x@x0001/_primary.vhd
core8051_lcd1602/simulation/postsynth/@x@y@x@x0002/verilog.psm
core8051_lcd1602/simulation/postsynth/@x@y@x@x0002/_primary.dat
core8051_lcd1602/simulation/postsynth/@x@y@x@x0002/_primary.dbs
core8051_lcd1602/simulation/postsynth/@x@y@x@x0002/_primary.vhd
core8051_lcd1602/simulation/postsynth/@x@y@x@x0003/verilog.psm
core8051_lcd1602/simulation/postsynth/@x@y@x@x0003/_primary.dat
core8051_lcd1602/simulation/postsynth/@x@y@x@x0003/_primary.dbs
core8051_lcd1602/simulation/postsynth/@x@y@x@x0003/_primary.vhd
core8051_lcd1602/simulation/postsynth/@x@y@x@x0004/verilog.psm
core8051_lcd1602/simulation/postsynth/@x@y@x@x0004/_primary.dat
core8051_lcd1602/simulation/postsynth/@x@y@x@x0004/_primary.dbs
core8051_lcd1602/simulation/postsynth/@x@y@x@x0004/_primary.vhd
core8051_lcd1602/simul

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