文件名称:src
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- 上传时间:2012-11-16
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文件大小:148.24kb
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a H.264/AVC Baseline Decoder,用FPGA来实现的编码和解码等等内容-a H.264/AVC Baseline Decoder, use FPGA to realize the encoding and decoding the content and so on
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下载文件列表
src/Beha_BitStream_ram.v
src/BitStream_buffer.v
src/BitStream_controller.v
src/bitstream_gclk_gen.v
src/BitStream_parser_FSM_gating.v
src/bs_decoding.v
src/cavlc_consumed_bits_decoding.v
src/cavlc_decoder.v
src/CodedBlockPattern_decoding.v
src/CVS/Entries
src/CVS/Repository
src/CVS/Root
src/CVS
src/dependent_variable_decoding.v
src/DF_mem_ctrl.v
src/DF_pipeline.v
src/DF_reg_ctrl.v
src/DF_top.v
src/end_of_blk_decoding.v
src/exp_golomb_decoding.v
src/ext_frame_RAM0_wrapper.v
src/ext_frame_RAM1_wrapper.v
src/ext_RAM_ctrl.v
src/heading_one_detector.v
src/hybrid_pipeline_ctrl.v
src/Inter_mv_decoding.v
src/Inter_pred_CPE.v
src/Inter_pred_LPE.v
src/Inter_pred_pipeline.v
src/Inter_pred_reg_ctrl.v
src/Inter_pred_sliding_window.v
src/Inter_pred_top.v
src/Intra4x4_PredMode_decoding.v
src/Intra_pred_PE.v
src/Intra_pred_pipeline.v
src/Intra_pred_reg_ctrl.v
src/Intra_pred_top.v
src/IQIT.v
src/level_decoding.v
src/nC_decoding.v
src/nova.v
src/nova_defines.v
src/nova_tb.v
src/NumCoeffTrailingOnes_decoding.v
src/pc_decoding.v
src/QP_decoding.v
src/ram_async_1r_sync_1w.v
src/ram_sync_1r_sync_1w.v
src/reconstruction.v
src/rec_DF_RAM_ctrl.v
src/rec_gclk_gen.v
src/run_decoding.v
src/sum.v
src/syntax_decoding.v
src/timescale.v
src/total_zeros_decoding.v
src
src/BitStream_buffer.v
src/BitStream_controller.v
src/bitstream_gclk_gen.v
src/BitStream_parser_FSM_gating.v
src/bs_decoding.v
src/cavlc_consumed_bits_decoding.v
src/cavlc_decoder.v
src/CodedBlockPattern_decoding.v
src/CVS/Entries
src/CVS/Repository
src/CVS/Root
src/CVS
src/dependent_variable_decoding.v
src/DF_mem_ctrl.v
src/DF_pipeline.v
src/DF_reg_ctrl.v
src/DF_top.v
src/end_of_blk_decoding.v
src/exp_golomb_decoding.v
src/ext_frame_RAM0_wrapper.v
src/ext_frame_RAM1_wrapper.v
src/ext_RAM_ctrl.v
src/heading_one_detector.v
src/hybrid_pipeline_ctrl.v
src/Inter_mv_decoding.v
src/Inter_pred_CPE.v
src/Inter_pred_LPE.v
src/Inter_pred_pipeline.v
src/Inter_pred_reg_ctrl.v
src/Inter_pred_sliding_window.v
src/Inter_pred_top.v
src/Intra4x4_PredMode_decoding.v
src/Intra_pred_PE.v
src/Intra_pred_pipeline.v
src/Intra_pred_reg_ctrl.v
src/Intra_pred_top.v
src/IQIT.v
src/level_decoding.v
src/nC_decoding.v
src/nova.v
src/nova_defines.v
src/nova_tb.v
src/NumCoeffTrailingOnes_decoding.v
src/pc_decoding.v
src/QP_decoding.v
src/ram_async_1r_sync_1w.v
src/ram_sync_1r_sync_1w.v
src/reconstruction.v
src/rec_DF_RAM_ctrl.v
src/rec_gclk_gen.v
src/run_decoding.v
src/sum.v
src/syntax_decoding.v
src/timescale.v
src/total_zeros_decoding.v
src
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