文件名称:ide
-
所属分类:
- 标签属性:
- 上传时间:2012-11-16
-
文件大小:5.54mb
-
已下载:0次
-
提 供 者:
-
相关连接:无下载说明:别用迅雷下载,失败请重下,重下不扣分!
介绍说明--下载内容来自于网络,使用问题请自行百度
ide 的HDL描述.有接口和时续-HDL descr iption of the ide. when there is interface and continued
(系统自动生成,下载前可以参看下载内容)
下载文件列表
ata
...\bench
...\.....\CVS
...\.....\...\Entries
...\.....\...\Repository
...\.....\...\Root
...\.....\verilog
...\.....\.......\ata_device.v
...\.....\.......\CVS
...\.....\.......\...\Entries
...\.....\.......\...\Repository
...\.....\.......\...\Root
...\.....\.......\tests.v
...\.....\.......\test_bench_top.v
...\.....\.......\wb_mast_model.v
...\.....\.......\wb_model_defines.v
...\.....\.......\wb_slv_model.v
...\.....\vhdl
...\.....\....\CVS
...\.....\....\...\Entries
...\.....\....\...\Repository
...\.....\....\...\Root
...\CVS
...\...\Entries
...\...\Repository
...\...\Root
...\doc
...\...\CVS
...\...\...\Entries
...\...\...\Repository
...\...\...\Root
...\...\preliminary_ata_core.pdf
...\...\src
...\...\...\ata_core.doc
...\...\...\CVS
...\...\...\...\Entries
...\...\...\...\Repository
...\...\...\...\Root
...\documentation
...\.............\CVS
...\.............\...\Entries
...\.............\...\Repository
...\.............\...\Root
...\rtl
...\...\CVS
...\...\...\Entries
...\...\...\Repository
...\...\...\Root
...\...\verilog
...\...\.......\CVS
...\...\.......\...\Entries
...\...\.......\...\Repository
...\...\.......\...\Root
...\...\.......\ocidec-1
...\...\.......\........\atahost_controller.v
...\...\.......\........\atahost_pio_tctrl.v
...\...\.......\........\atahost_top.v
...\...\.......\........\atahost_wb_slave.v
...\...\.......\........\CVS
...\...\.......\........\...\Entries
...\...\.......\........\...\Repository
...\...\.......\........\...\Root
...\...\.......\........\revision_history.txt
...\...\.......\........\ro_cnt.v
...\...\.......\........\timescale.v
...\...\.......\........\ud_cnt.v
...\...\.......\ocidec-2
...\...\.......\........\atahost_controller.v
...\...\.......\........\atahost_pio_actrl.v
...\...\.......\........\atahost_pio_tctrl.v
...\...\.......\........\atahost_top.v
...\...\.......\........\atahost_wb_slave.v
...\...\.......\........\CVS
...\...\.......\........\...\Entries
...\...\.......\........\...\Repository
...\...\.......\........\...\Root
...\...\.......\........\revision_history.txt
...\...\.......\........\ro_cnt.v
...\...\.......\........\timescale.v
...\...\.......\........\ud_cnt.v
...\...\vhdl
...\...\....\CVS
...\...\....\...\Entries
...\...\....\...\Repository
...\...\....\...\Root
...\...\....\ocidec1
...\...\....\.......\atahost_controller.vhd
...\...\....\.......\atahost_pio_tctrl.vhd
...\...\....\.......\atahost_top.vhd
...\...\....\.......\atahost_wb_slave.vhd
...\...\....\.......\CVS
...\...\....\.......\...\Entries
...\...\....\.......\...\Repository
...\...\....\.......\...\Root
...\...\....\.......\revision_history.txt
...\...\....\.......\ro_cnt.vhd
...\...\....\.......\ud_cnt.vhd
...\...\....\ocidec2
...\...\....\.......\atahost_controller.vhd
...\...\....\.......\atahost_pio_actrl.vhd
...\bench
...\.....\CVS
...\.....\...\Entries
...\.....\...\Repository
...\.....\...\Root
...\.....\verilog
...\.....\.......\ata_device.v
...\.....\.......\CVS
...\.....\.......\...\Entries
...\.....\.......\...\Repository
...\.....\.......\...\Root
...\.....\.......\tests.v
...\.....\.......\test_bench_top.v
...\.....\.......\wb_mast_model.v
...\.....\.......\wb_model_defines.v
...\.....\.......\wb_slv_model.v
...\.....\vhdl
...\.....\....\CVS
...\.....\....\...\Entries
...\.....\....\...\Repository
...\.....\....\...\Root
...\CVS
...\...\Entries
...\...\Repository
...\...\Root
...\doc
...\...\CVS
...\...\...\Entries
...\...\...\Repository
...\...\...\Root
...\...\preliminary_ata_core.pdf
...\...\src
...\...\...\ata_core.doc
...\...\...\CVS
...\...\...\...\Entries
...\...\...\...\Repository
...\...\...\...\Root
...\documentation
...\.............\CVS
...\.............\...\Entries
...\.............\...\Repository
...\.............\...\Root
...\rtl
...\...\CVS
...\...\...\Entries
...\...\...\Repository
...\...\...\Root
...\...\verilog
...\...\.......\CVS
...\...\.......\...\Entries
...\...\.......\...\Repository
...\...\.......\...\Root
...\...\.......\ocidec-1
...\...\.......\........\atahost_controller.v
...\...\.......\........\atahost_pio_tctrl.v
...\...\.......\........\atahost_top.v
...\...\.......\........\atahost_wb_slave.v
...\...\.......\........\CVS
...\...\.......\........\...\Entries
...\...\.......\........\...\Repository
...\...\.......\........\...\Root
...\...\.......\........\revision_history.txt
...\...\.......\........\ro_cnt.v
...\...\.......\........\timescale.v
...\...\.......\........\ud_cnt.v
...\...\.......\ocidec-2
...\...\.......\........\atahost_controller.v
...\...\.......\........\atahost_pio_actrl.v
...\...\.......\........\atahost_pio_tctrl.v
...\...\.......\........\atahost_top.v
...\...\.......\........\atahost_wb_slave.v
...\...\.......\........\CVS
...\...\.......\........\...\Entries
...\...\.......\........\...\Repository
...\...\.......\........\...\Root
...\...\.......\........\revision_history.txt
...\...\.......\........\ro_cnt.v
...\...\.......\........\timescale.v
...\...\.......\........\ud_cnt.v
...\...\vhdl
...\...\....\CVS
...\...\....\...\Entries
...\...\....\...\Repository
...\...\....\...\Root
...\...\....\ocidec1
...\...\....\.......\atahost_controller.vhd
...\...\....\.......\atahost_pio_tctrl.vhd
...\...\....\.......\atahost_top.vhd
...\...\....\.......\atahost_wb_slave.vhd
...\...\....\.......\CVS
...\...\....\.......\...\Entries
...\...\....\.......\...\Repository
...\...\....\.......\...\Root
...\...\....\.......\revision_history.txt
...\...\....\.......\ro_cnt.vhd
...\...\....\.......\ud_cnt.vhd
...\...\....\ocidec2
...\...\....\.......\atahost_controller.vhd
...\...\....\.......\atahost_pio_actrl.vhd
本网站为编程资源及源代码搜集、介绍的搜索网站,版权归原作者所有! 粤ICP备11031372号
1999-2046 搜珍网 All Rights Reserved.