比特序列传送模块

把输入的八位比特数据 做循环后每个比特输出 详细请看英文描述-•　To create Verilog-HDL modules written in the RTL style appropriate for both simulation and synthesis, for the various component parts of an Asynchronous Serial Data Transmitter.

•　To verify the correct behaviour of each component part by means of simulation.

•　To construct a top-level module corresponding to the Asynchronous Serial Data Transmitter, making use of the component parts developed above, and any additional behavioural elements which may be required.

•　To verify the correct operation of the top-level design by means of simulation using a Verilog-HDL test-fixture.

•　To automatically create a hierarchical logic diagram for the Asynchronous Serial Data Transmitter, generated using a Logic Synthesis tool.