4bitcomp\4bitcomp.prj
4bitcomp/component/
4bitcomp/constraint/
4bitcomp/coreconsole/
4bitcomp/designer/
4bitcomp/designer/impl1/
4bitcomp/designer/impl1/simulation/
4bitcomp\hdl\4bitcomp.vhd
4bitcomp/phy_synthesis/
4bitcomp\simulation\modelsim.ini
4bitcomp\simulation\modelsim.log
4bitcomp\simulation\presynth\a_4_bit_comparator\arch.dat
4bitcomp\simulation\presynth\a_4_bit_comparator\arch.dbs
4bitcomp\simulation\presynth\a_4_bit_comparator\arch.psm
4bitcomp\simulation\presynth\a_4_bit_comparator\_primary.dat
4bitcomp\simulation\presynth\a_4_bit_comparator\_primary.dbs
4bitcomp\simulation\presynth\stimulus\stimulator.dat
4bitcomp\simulation\presynth\stimulus\stimulator.dbs
4bitcomp\simulation\presynth\stimulus\stimulator.psm
4bitcomp\simulation\presynth\stimulus\_primary.dat
4bitcomp\simulation\presynth\stimulus\_primary.dbs
4bitcomp\simulation\presynth\testbench\tbgeneratedcode.dat
4bitcomp\simulation\presynth\testbench\tbgeneratedcode.dbs
4bitcomp\simulation\presynth\testbench\tbgeneratedcode.psm
4bitcomp\simulation\presynth\testbench\_primary.dat
4bitcomp\simulation\presynth\testbench\_primary.dbs
4bitcomp\simulation\presynth\_info
4bitcomp/simulation/presynth/_temp/
4bitcomp\simulation\run.do
4bitcomp\simulation\tb.log
4bitcomp\simulation\vsim.wlf
4bitcomp\smartgen\smartgen.aws
4bitcomp\stimulus\a_4_bit_comparator.dsk
4bitcomp\stimulus\a_4_bit_comparator.hpj
4bitcomp\stimulus\BtimErrors.log
4bitcomp\stimulus\files_to_build.txt
4bitcomp\stimulus\ModelUnderTest_tbench.btim
4bitcomp\stimulus\ModelUnderTest_tbench.vhd
4bitcomp\stimulus\waveperl.log
4bitcomp/synthesis/
4bitcomp/viewdraw/sch/
4bitcomp/viewdraw/sym/
4bitcomp\viewdraw\vf\project.lst
4bitcomp\viewdraw\viewdraw.ini
4bitcomp/viewdraw/wir/