文件名称:jishu60
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verilog实例,用verilog模块例化方式设计一个60S的定时器。-verilog example verilog modules were used to design a way of timer 60S.
相关搜索: Verilog 定时器
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下载文件列表
jishu60/block1.v
jishu60/block1.bsf
jishu60/jishi.v
jishu60/jishi.bsf
jishu60/Dec7s.v
jishu60/Dec7s.bsf
jishu60/jishu60.qpf
jishu60/jishu60.qsf
jishu60/db/jishu60.db_info
jishu60/db/jishu60.cbx.xml
jishu60/db/jishu60.hif
jishu60/db/jishu60.(1).cnf.cdb
jishu60/db/jishu60.(1).cnf.hdb
jishu60/db/jishu60.(2).cnf.cdb
jishu60/db/jishu60.(2).cnf.hdb
jishu60/db/jishu60.(0).cnf.cdb
jishu60/db/jishu60.(0).cnf.hdb
jishu60/db/jishu60.(3).cnf.cdb
jishu60/db/jishu60.(3).cnf.hdb
jishu60/db/jishu60.hier_info
jishu60/db/jishu60.psp
jishu60/db/jishu60.dbp
jishu60/db/jishu60.(4).cnf.cdb
jishu60/db/jishu60.(4).cnf.hdb
jishu60/db/jishu60.syn_hier_info
jishu60/db/jishu60.sim.qmsg
jishu60/db/jishu60.sim.hdb
jishu60/db/jishu60.eds_overflow
jishu60/db/jishu60.sim.vwf
jishu60/db/jishu60.sim.rdb
jishu60/db/wed.zsf
jishu60/db/jishu60.map.qmsg
jishu60/db/jishu60.rtlv_sg.cdb
jishu60/db/jishu60.rtlv.hdb
jishu60/db/jishu60.rtlv_sg_swap.cdb
jishu60/db/jishu60.pre_map.hdb
jishu60/db/jishu60.pre_map.cdb
jishu60/db/jishu60.map.logdb
jishu60/db/jishu60.sgdiff.cdb
jishu60/db/jishu60.sgdiff.hdb
jishu60/db/jishu60.sld_design_entry_dsc.sci
jishu60/db/jishu60.map.cdb
jishu60/db/jishu60.map.hdb
jishu60/db/jishu60.fit.qmsg
jishu60/db/jishu60.cmp.logdb
jishu60/db/jishu60.asm.qmsg
jishu60/db/jishu60.tan.qmsg
jishu60/db/jishu60.cmp.tdb
jishu60/db/jishu60.cmp0.ddb
jishu60/db/jishu60.cmp.cdb
jishu60/db/jishu60.cmp.hdb
jishu60/db/jishu60.cmp.rdb
jishu60/db/jishu60.sld_design_entry.sci
jishu60/db/jishu60.eco.cdb
jishu60/jishu60.v
jishu60/jishu60.map.rpt
jishu60/jishu60.flow.rpt
jishu60/jishu60.map.summary
jishu60/jishu60.pin
jishu60/jishu60.fit.rpt
jishu60/jishu60.fit.summary
jishu60/jishu60.pof
jishu60/jishu60.asm.rpt
jishu60/jishu60.tan.summary
jishu60/jishu60.tan.rpt
jishu60/jishu60.done
jishu60/jishu60.vwf
jishu60/jishu60.sim.rpt
jishu60/jishu60.qws
jishu60/db
jishu60
jishu60/block1.bsf
jishu60/jishi.v
jishu60/jishi.bsf
jishu60/Dec7s.v
jishu60/Dec7s.bsf
jishu60/jishu60.qpf
jishu60/jishu60.qsf
jishu60/db/jishu60.db_info
jishu60/db/jishu60.cbx.xml
jishu60/db/jishu60.hif
jishu60/db/jishu60.(1).cnf.cdb
jishu60/db/jishu60.(1).cnf.hdb
jishu60/db/jishu60.(2).cnf.cdb
jishu60/db/jishu60.(2).cnf.hdb
jishu60/db/jishu60.(0).cnf.cdb
jishu60/db/jishu60.(0).cnf.hdb
jishu60/db/jishu60.(3).cnf.cdb
jishu60/db/jishu60.(3).cnf.hdb
jishu60/db/jishu60.hier_info
jishu60/db/jishu60.psp
jishu60/db/jishu60.dbp
jishu60/db/jishu60.(4).cnf.cdb
jishu60/db/jishu60.(4).cnf.hdb
jishu60/db/jishu60.syn_hier_info
jishu60/db/jishu60.sim.qmsg
jishu60/db/jishu60.sim.hdb
jishu60/db/jishu60.eds_overflow
jishu60/db/jishu60.sim.vwf
jishu60/db/jishu60.sim.rdb
jishu60/db/wed.zsf
jishu60/db/jishu60.map.qmsg
jishu60/db/jishu60.rtlv_sg.cdb
jishu60/db/jishu60.rtlv.hdb
jishu60/db/jishu60.rtlv_sg_swap.cdb
jishu60/db/jishu60.pre_map.hdb
jishu60/db/jishu60.pre_map.cdb
jishu60/db/jishu60.map.logdb
jishu60/db/jishu60.sgdiff.cdb
jishu60/db/jishu60.sgdiff.hdb
jishu60/db/jishu60.sld_design_entry_dsc.sci
jishu60/db/jishu60.map.cdb
jishu60/db/jishu60.map.hdb
jishu60/db/jishu60.fit.qmsg
jishu60/db/jishu60.cmp.logdb
jishu60/db/jishu60.asm.qmsg
jishu60/db/jishu60.tan.qmsg
jishu60/db/jishu60.cmp.tdb
jishu60/db/jishu60.cmp0.ddb
jishu60/db/jishu60.cmp.cdb
jishu60/db/jishu60.cmp.hdb
jishu60/db/jishu60.cmp.rdb
jishu60/db/jishu60.sld_design_entry.sci
jishu60/db/jishu60.eco.cdb
jishu60/jishu60.v
jishu60/jishu60.map.rpt
jishu60/jishu60.flow.rpt
jishu60/jishu60.map.summary
jishu60/jishu60.pin
jishu60/jishu60.fit.rpt
jishu60/jishu60.fit.summary
jishu60/jishu60.pof
jishu60/jishu60.asm.rpt
jishu60/jishu60.tan.summary
jishu60/jishu60.tan.rpt
jishu60/jishu60.done
jishu60/jishu60.vwf
jishu60/jishu60.sim.rpt
jishu60/jishu60.qws
jishu60/db
jishu60
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