文件名称:AVR_UARTFPGA
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- 上传时间:2012-11-16
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文件大小:1.96mb
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基于VHDL(verilog)语言的UART的设计与实现。全面模仿AVR的UART功能,与AVR直接实现接口调试。资料全面完整。-Based on VHDL (verilog) Language Design and Implementation of UART. UART fully mimic the function of AVR, and AVR debugging interface directly to achieve. Overall integrity of the information.
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读我.txt
UART设计文档.pdf
fpga/V0p10/uart.qpf
fpga/V0p10/uart.qsf
fpga/V0p10/uart_description.txt
fpga/V0p10/uart.map.smsg
fpga/V0p10/uart.map.summary
fpga/V0p10/uart.pin
fpga/V0p10/uart.fit.smsg
fpga/V0p10/uart.fit.summary
fpga/V0p10/uart.sof
fpga/V0p10/uart.pof
fpga/V0p10/uart.tan.summary
fpga/V0p10/uart.done
fpga/V0p10/uart.dpf
fpga/V0p10/uart.cdf
fpga/V0p10/top.bsf
fpga/V0p10/src/txd.v
fpga/V0p10/src/uart.v
fpga/V0p10/src/divider.v
fpga/V0p10/src/ebi.v
fpga/V0p10/src/rxd.v
fpga/V0p10/src/top.v
fpga/V0p10/testbench/vsim_stacktrace.vstf
fpga/V0p10/testbench/transcript
fpga/V0p10/testbench/vish_stacktrace.vstf
fpga/V0p10/testbench/top_tb.v
fpga/V0p10/testbench/ModelSim.jpg
fpga/V0p10/testbench/tcl_stacktrace.txt
fpga/V0p10/testbench/vsim.wlf
fpga/V0p10/testbench/uart.mpf
fpga/V0p10/testbench/uart.cr.mti
fpga/V0p10/testbench/cycloneII_v/_info
fpga/V0p10/testbench/work/_info
fpga/V0p10/testbench/work/uart/_primary.vhd
fpga/V0p10/testbench/work/uart/_primary.dat
fpga/V0p10/testbench/work/uart/verilog.asm
fpga/V0p10/testbench/work/rxd/_primary.vhd
fpga/V0p10/testbench/work/rxd/_primary.dat
fpga/V0p10/testbench/work/rxd/verilog.asm
fpga/V0p10/testbench/work/txd/_primary.vhd
fpga/V0p10/testbench/work/txd/_primary.dat
fpga/V0p10/testbench/work/txd/verilog.asm
fpga/V0p10/testbench/work/top/_primary.vhd
fpga/V0p10/testbench/work/top/_primary.dat
fpga/V0p10/testbench/work/top/verilog.asm
fpga/V0p10/testbench/work/ebi/_primary.vhd
fpga/V0p10/testbench/work/ebi/_primary.dat
fpga/V0p10/testbench/work/ebi/verilog.asm
fpga/V0p10/testbench/work/division/_primary.vhd
fpga/V0p10/testbench/work/division/_primary.dat
fpga/V0p10/testbench/work/division/verilog.asm
fpga/V0p10/testbench/work/divider/_primary.vhd
fpga/V0p10/testbench/work/divider/_primary.dat
fpga/V0p10/testbench/work/divider/verilog.asm
fpga/V0p10/testbench/work/top_tb/_primary.vhd
fpga/V0p10/testbench/work/top_tb/_primary.dat
fpga/V0p10/testbench/work/top_tb/verilog.asm
fpga/V0p10/uart.map.rpt
fpga/V0p10/uart.fit.rpt
fpga/V0p10/uart.asm.rpt
fpga/V0p10/uart.tan.rpt
fpga/V0p10/uart.flow.rpt
fpga/V0p10/uart.qws
Mcu/UartTest/stdinc.h
Mcu/UartTest/UartCtrl.c
Mcu/UartTest/UartTest.eww
Mcu/UartTest/UartTest.ewp
Mcu/UartTest/UartTest.ewd
Mcu/UartTest/UartTest.dep
Mcu/UartTest/main.c
Mcu/UartTest/FpgaInc.h
Mcu/UartTest/UartCtrl.h
Mcu/UartTest/settings/test.cspy.bat
Mcu/UartTest/settings/test.dni
Mcu/UartTest/settings/test.wsdt
Mcu/UartTest/settings/test.dbgdt
Mcu/UartTest/settings/UartTest.cspy.bat
Mcu/UartTest/settings/UartTest.wsdt
Mcu/UartTest/settings/UartTest.dni
fpga/V0p10/testbench/work/uart
fpga/V0p10/testbench/work/rxd
fpga/V0p10/testbench/work/txd
fpga/V0p10/testbench/work/top
fpga/V0p10/testbench/work/ebi
fpga/V0p10/testbench/work/division
fpga/V0p10/testbench/work/divider
fpga/V0p10/testbench/work/top_tb
fpga/V0p10/testbench/work/_temp
fpga/V0p10/testbench/cycloneII_v
fpga/V0p10/testbench/work
Mcu/UartTest/Debug/Exe
Mcu/UartTest/Debug/Obj
Mcu/UartTest/Debug/List
fpga/V0p10/src
fpga/V0p10/testbench
fpga/V0p10/db
Mcu/UartTest/settings
Mcu/UartTest/Debug
fpga/V0p10
Mcu/UartTest
创造力电子开发网
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Mcu
创造力电子开发网/首页-创造力电子开发网.url
创造力电子开发网/登录-创造力电子开发网.url
创造力电子开发网.url
读我.txt
UART设计文档.pdf
fpga/V0p10/uart.qpf
fpga/V0p10/uart.qsf
fpga/V0p10/uart_description.txt
fpga/V0p10/uart.map.smsg
fpga/V0p10/uart.map.summary
fpga/V0p10/uart.pin
fpga/V0p10/uart.fit.smsg
fpga/V0p10/uart.fit.summary
fpga/V0p10/uart.sof
fpga/V0p10/uart.pof
fpga/V0p10/uart.tan.summary
fpga/V0p10/uart.done
fpga/V0p10/uart.dpf
fpga/V0p10/uart.cdf
fpga/V0p10/top.bsf
fpga/V0p10/src/txd.v
fpga/V0p10/src/uart.v
fpga/V0p10/src/divider.v
fpga/V0p10/src/ebi.v
fpga/V0p10/src/rxd.v
fpga/V0p10/src/top.v
fpga/V0p10/testbench/vsim_stacktrace.vstf
fpga/V0p10/testbench/transcript
fpga/V0p10/testbench/vish_stacktrace.vstf
fpga/V0p10/testbench/top_tb.v
fpga/V0p10/testbench/ModelSim.jpg
fpga/V0p10/testbench/tcl_stacktrace.txt
fpga/V0p10/testbench/vsim.wlf
fpga/V0p10/testbench/uart.mpf
fpga/V0p10/testbench/uart.cr.mti
fpga/V0p10/testbench/cycloneII_v/_info
fpga/V0p10/testbench/work/_info
fpga/V0p10/testbench/work/uart/_primary.vhd
fpga/V0p10/testbench/work/uart/_primary.dat
fpga/V0p10/testbench/work/uart/verilog.asm
fpga/V0p10/testbench/work/rxd/_primary.vhd
fpga/V0p10/testbench/work/rxd/_primary.dat
fpga/V0p10/testbench/work/rxd/verilog.asm
fpga/V0p10/testbench/work/txd/_primary.vhd
fpga/V0p10/testbench/work/txd/_primary.dat
fpga/V0p10/testbench/work/txd/verilog.asm
fpga/V0p10/testbench/work/top/_primary.vhd
fpga/V0p10/testbench/work/top/_primary.dat
fpga/V0p10/testbench/work/top/verilog.asm
fpga/V0p10/testbench/work/ebi/_primary.vhd
fpga/V0p10/testbench/work/ebi/_primary.dat
fpga/V0p10/testbench/work/ebi/verilog.asm
fpga/V0p10/testbench/work/division/_primary.vhd
fpga/V0p10/testbench/work/division/_primary.dat
fpga/V0p10/testbench/work/division/verilog.asm
fpga/V0p10/testbench/work/divider/_primary.vhd
fpga/V0p10/testbench/work/divider/_primary.dat
fpga/V0p10/testbench/work/divider/verilog.asm
fpga/V0p10/testbench/work/top_tb/_primary.vhd
fpga/V0p10/testbench/work/top_tb/_primary.dat
fpga/V0p10/testbench/work/top_tb/verilog.asm
fpga/V0p10/uart.map.rpt
fpga/V0p10/uart.fit.rpt
fpga/V0p10/uart.asm.rpt
fpga/V0p10/uart.tan.rpt
fpga/V0p10/uart.flow.rpt
fpga/V0p10/uart.qws
Mcu/UartTest/stdinc.h
Mcu/UartTest/UartCtrl.c
Mcu/UartTest/UartTest.eww
Mcu/UartTest/UartTest.ewp
Mcu/UartTest/UartTest.ewd
Mcu/UartTest/UartTest.dep
Mcu/UartTest/main.c
Mcu/UartTest/FpgaInc.h
Mcu/UartTest/UartCtrl.h
Mcu/UartTest/settings/test.cspy.bat
Mcu/UartTest/settings/test.dni
Mcu/UartTest/settings/test.wsdt
Mcu/UartTest/settings/test.dbgdt
Mcu/UartTest/settings/UartTest.cspy.bat
Mcu/UartTest/settings/UartTest.wsdt
Mcu/UartTest/settings/UartTest.dni
fpga/V0p10/testbench/work/uart
fpga/V0p10/testbench/work/rxd
fpga/V0p10/testbench/work/txd
fpga/V0p10/testbench/work/top
fpga/V0p10/testbench/work/ebi
fpga/V0p10/testbench/work/division
fpga/V0p10/testbench/work/divider
fpga/V0p10/testbench/work/top_tb
fpga/V0p10/testbench/work/_temp
fpga/V0p10/testbench/cycloneII_v
fpga/V0p10/testbench/work
Mcu/UartTest/Debug/Exe
Mcu/UartTest/Debug/Obj
Mcu/UartTest/Debug/List
fpga/V0p10/src
fpga/V0p10/testbench
fpga/V0p10/db
Mcu/UartTest/settings
Mcu/UartTest/Debug
fpga/V0p10
Mcu/UartTest
创造力电子开发网
fpga
Mcu
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