文件名称:i2c
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- 上传时间:2012-11-16
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文件大小:2.27mb
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下载文件列表
i2c/bench/CVS/Entries
i2c/bench/CVS/Repository
i2c/bench/CVS/Root
i2c/bench/verilog/CVS/Entries
i2c/bench/verilog/CVS/Repository
i2c/bench/verilog/CVS/Root
i2c/bench/verilog/i2c_slave_model.v
i2c/bench/verilog/i2c_slave_model.v.bak
i2c/bench/verilog/spi_slave_model.v
i2c/bench/verilog/spi_slave_model.v.bak
i2c/bench/verilog/tst_bench_top.v
i2c/bench/verilog/tst_bench_top.v.bak
i2c/bench/verilog/waveperl.log
i2c/bench/verilog/wb_master_model.v
i2c/bench/verilog/wb_master_model.v.bak
i2c/CVS/Entries
i2c/CVS/Repository
i2c/CVS/Root
i2c/doc/CVS/Entries
i2c/doc/CVS/Repository
i2c/doc/CVS/Root
i2c/doc/i2c_specs.pdf
i2c/doc/src/CVS/Entries
i2c/doc/src/CVS/Repository
i2c/doc/src/CVS/Root
i2c/doc/src/I2C_specs.doc
i2c/rtl/CVS/Entries
i2c/rtl/CVS/Repository
i2c/rtl/CVS/Root
i2c/rtl/verilog/CVS/Entries
i2c/rtl/verilog/CVS/Repository
i2c/rtl/verilog/CVS/Root
i2c/rtl/verilog/i2c_master_bit_ctrl.v
i2c/rtl/verilog/i2c_master_bit_ctrl.v.bak
i2c/rtl/verilog/i2c_master_byte_ctrl.v
i2c/rtl/verilog/i2c_master_byte_ctrl.v.bak
i2c/rtl/verilog/i2c_master_defines.v
i2c/rtl/verilog/i2c_master_top.v
i2c/rtl/verilog/i2c_master_top.v.bak
i2c/rtl/verilog/timescale.v
i2c/rtl/verilog/waveperl.log
i2c/rtl/vhdl/CVS/Entries
i2c/rtl/vhdl/CVS/Repository
i2c/rtl/vhdl/CVS/Root
i2c/rtl/vhdl/I2C.VHD
i2c/rtl/vhdl/i2c_master_bit_ctrl.vhd
i2c/rtl/vhdl/i2c_master_byte_ctrl.vhd
i2c/rtl/vhdl/i2c_master_top.vhd
i2c/rtl/vhdl/readme
i2c/rtl/vhdl/tst_ds1621.vhd
i2c/sim/CVS/Entries
i2c/sim/CVS/Repository
i2c/sim/CVS/Root
i2c/sim/i2c.cr.mti
i2c/sim/i2c.mpf
i2c/sim/i2c_verilog/CVS/Entries
i2c/sim/i2c_verilog/CVS/Repository
i2c/sim/i2c_verilog/CVS/Root
i2c/sim/i2c_verilog/run/bench.vcd
i2c/sim/i2c_verilog/run/CVS/Entries
i2c/sim/i2c_verilog/run/CVS/Repository
i2c/sim/i2c_verilog/run/CVS/Root
i2c/sim/i2c_verilog/run/INCA_libs/CVS/Entries
i2c/sim/i2c_verilog/run/INCA_libs/CVS/Repository
i2c/sim/i2c_verilog/run/INCA_libs/CVS/Root
i2c/sim/i2c_verilog/run/ncverilog.key
i2c/sim/i2c_verilog/run/ncverilog.log
i2c/sim/i2c_verilog/run/run
i2c/sim/i2c_verilog/run/waves/CVS/Entries
i2c/sim/i2c_verilog/run/waves/CVS/Repository
i2c/sim/i2c_verilog/run/waves/CVS/Root
i2c/sim/vsim.wlf
i2c/sim/work/@m@a@x@i@i_@p@r@i@m_@d@f@f@e/verilog.asm
i2c/sim/work/@m@a@x@i@i_@p@r@i@m_@d@f@f@e/_primary.dat
i2c/sim/work/@m@a@x@i@i_@p@r@i@m_@d@f@f@e/_primary.vhd
i2c/sim/work/delay/verilog.asm
i2c/sim/work/delay/_primary.dat
i2c/sim/work/delay/_primary.vhd
i2c/sim/work/i2c_master_bit_ctrl/verilog.asm
i2c/sim/work/i2c_master_bit_ctrl/_primary.dat
i2c/sim/work/i2c_master_bit_ctrl/_primary.vhd
i2c/sim/work/i2c_master_byte_ctrl/verilog.asm
i2c/sim/work/i2c_master_byte_ctrl/_primary.dat
i2c/sim/work/i2c_master_byte_ctrl/_primary.vhd
i2c/sim/work/i2c_master_top/verilog.asm
i2c/sim/work/i2c_master_top/_primary.dat
i2c/sim/work/i2c_master_top/_primary.vhd
i2c/sim/work/i2c_slave_model/verilog.asm
i2c/sim/work/i2c_slave_model/_primary.dat
i2c/sim/work/i2c_slave_model/_primary.vhd
i2c/sim/work/maxii_and1/verilog.asm
i2c/sim/work/maxii_and1/_primary.dat
i2c/sim/work/maxii_and1/_primary.vhd
i2c/sim/work/maxii_and16/verilog.asm
i2c/sim/work/maxii_and16/_primary.dat
i2c/sim/work/maxii_and16/_primary.vhd
i2c/sim/work/maxii_asynch_lcell/verilog.asm
i2c/sim/work/maxii_asynch_lcell/_primary.dat
i2c/sim/work/maxii_asynch_lcell/_primary.vhd
i2c/sim/work/maxii_b17mux21/verilog.asm
i2c/sim/work/maxii_b17mux21/_primary.dat
i2c/sim/work/maxii_b17mux21/_primary.vhd
i2c/sim/work/maxii_b5mux21/verilog.asm
i2c/sim/work/maxii_b5mux21/_primary.dat
i2c/sim/work/maxii_b5mux21/_primary.vhd
i2c/sim/work/maxii_bmux21/verilog.asm
i2c/sim/work/maxii_bmux21/_primary.dat
i2c/sim/work/maxii_bmux21/_primary.vhd
i2c/sim/work/maxii_dffe/verilog.asm
i2c/sim/work/maxii_dffe/_primary.dat
i2c/sim/work/maxii_dffe/_primary.vhd
i2c/sim/work/maxii_io/verilog.asm
i2c/sim/work/maxii_io/_primary.dat
i2c/sim/work/maxii_io/_primary.vhd
i2c/sim/work/maxii_latch/verilog.asm
i2c/sim/work/maxii_latch/_primary.dat
i2c/sim/work/maxii_latch/_primary.vhd
i2c/sim/work/maxii_lcell/verilog.asm
i2c/sim/work/maxii_lcell/_primary.dat
i2c/sim/work/maxii_lcell/_primary.vhd
i2c/sim/work/maxii_lcell_register/verilog.asm
i2c/sim/work/maxii_lcell_register/_primary.dat
i2c/sim/work/maxii_lcell_register/_primary.vhd
i2c/sim/work/maxii_mux21/verilog.asm
i2c/sim/work/maxii_mux21/_primary.dat
i2c/sim/work/maxii_mux21/_primary.vhd
i2c/sim/work/maxii_mux41/verilog.asm
i2c/sim/work/maxii_mux41/_primary.dat
i2c/sim/work/maxii_mux41/_primary.vhd
i2c/sim/work/maxii_nmux21/verilog.asm
i2c/sim/work/maxii_nmux21/_primary.dat
i2c/sim/work/maxii_nmux21/_primary.vhd
i2c/sim/work/maxii_routing_wire/verilog.asm
i2c/sim/work/maxii_routing_wire/_primary.dat
i2c/sim/work/maxii_routing_wire/_primary.vhd
i2c/sim/work/maxii_ufm/verilog.asm
i2c/sim/work/maxii_ufm/_primary.dat
i2c/sim/work/maxii_ufm/_primary.vhd
i2c/sim/work/tst_bench_top/verilog.asm
i2c/sim/work/tst_bench_top/_primary.dat
i2c/sim/work/tst_bench_top/_primary.vhd
i2c/sim/work/wb_master_model/verilog.asm
i2c/sim/work/wb_master_model/_primary.dat
i2c/sim/work/wb_master_model/_primary.vhd
i2c/sim/work/_info
i2c/software/CVS/Entries
i2c/software/CVS/R
i2c/bench/CVS/Repository
i2c/bench/CVS/Root
i2c/bench/verilog/CVS/Entries
i2c/bench/verilog/CVS/Repository
i2c/bench/verilog/CVS/Root
i2c/bench/verilog/i2c_slave_model.v
i2c/bench/verilog/i2c_slave_model.v.bak
i2c/bench/verilog/spi_slave_model.v
i2c/bench/verilog/spi_slave_model.v.bak
i2c/bench/verilog/tst_bench_top.v
i2c/bench/verilog/tst_bench_top.v.bak
i2c/bench/verilog/waveperl.log
i2c/bench/verilog/wb_master_model.v
i2c/bench/verilog/wb_master_model.v.bak
i2c/CVS/Entries
i2c/CVS/Repository
i2c/CVS/Root
i2c/doc/CVS/Entries
i2c/doc/CVS/Repository
i2c/doc/CVS/Root
i2c/doc/i2c_specs.pdf
i2c/doc/src/CVS/Entries
i2c/doc/src/CVS/Repository
i2c/doc/src/CVS/Root
i2c/doc/src/I2C_specs.doc
i2c/rtl/CVS/Entries
i2c/rtl/CVS/Repository
i2c/rtl/CVS/Root
i2c/rtl/verilog/CVS/Entries
i2c/rtl/verilog/CVS/Repository
i2c/rtl/verilog/CVS/Root
i2c/rtl/verilog/i2c_master_bit_ctrl.v
i2c/rtl/verilog/i2c_master_bit_ctrl.v.bak
i2c/rtl/verilog/i2c_master_byte_ctrl.v
i2c/rtl/verilog/i2c_master_byte_ctrl.v.bak
i2c/rtl/verilog/i2c_master_defines.v
i2c/rtl/verilog/i2c_master_top.v
i2c/rtl/verilog/i2c_master_top.v.bak
i2c/rtl/verilog/timescale.v
i2c/rtl/verilog/waveperl.log
i2c/rtl/vhdl/CVS/Entries
i2c/rtl/vhdl/CVS/Repository
i2c/rtl/vhdl/CVS/Root
i2c/rtl/vhdl/I2C.VHD
i2c/rtl/vhdl/i2c_master_bit_ctrl.vhd
i2c/rtl/vhdl/i2c_master_byte_ctrl.vhd
i2c/rtl/vhdl/i2c_master_top.vhd
i2c/rtl/vhdl/readme
i2c/rtl/vhdl/tst_ds1621.vhd
i2c/sim/CVS/Entries
i2c/sim/CVS/Repository
i2c/sim/CVS/Root
i2c/sim/i2c.cr.mti
i2c/sim/i2c.mpf
i2c/sim/i2c_verilog/CVS/Entries
i2c/sim/i2c_verilog/CVS/Repository
i2c/sim/i2c_verilog/CVS/Root
i2c/sim/i2c_verilog/run/bench.vcd
i2c/sim/i2c_verilog/run/CVS/Entries
i2c/sim/i2c_verilog/run/CVS/Repository
i2c/sim/i2c_verilog/run/CVS/Root
i2c/sim/i2c_verilog/run/INCA_libs/CVS/Entries
i2c/sim/i2c_verilog/run/INCA_libs/CVS/Repository
i2c/sim/i2c_verilog/run/INCA_libs/CVS/Root
i2c/sim/i2c_verilog/run/ncverilog.key
i2c/sim/i2c_verilog/run/ncverilog.log
i2c/sim/i2c_verilog/run/run
i2c/sim/i2c_verilog/run/waves/CVS/Entries
i2c/sim/i2c_verilog/run/waves/CVS/Repository
i2c/sim/i2c_verilog/run/waves/CVS/Root
i2c/sim/vsim.wlf
i2c/sim/work/@m@a@x@i@i_@p@r@i@m_@d@f@f@e/verilog.asm
i2c/sim/work/@m@a@x@i@i_@p@r@i@m_@d@f@f@e/_primary.dat
i2c/sim/work/@m@a@x@i@i_@p@r@i@m_@d@f@f@e/_primary.vhd
i2c/sim/work/delay/verilog.asm
i2c/sim/work/delay/_primary.dat
i2c/sim/work/delay/_primary.vhd
i2c/sim/work/i2c_master_bit_ctrl/verilog.asm
i2c/sim/work/i2c_master_bit_ctrl/_primary.dat
i2c/sim/work/i2c_master_bit_ctrl/_primary.vhd
i2c/sim/work/i2c_master_byte_ctrl/verilog.asm
i2c/sim/work/i2c_master_byte_ctrl/_primary.dat
i2c/sim/work/i2c_master_byte_ctrl/_primary.vhd
i2c/sim/work/i2c_master_top/verilog.asm
i2c/sim/work/i2c_master_top/_primary.dat
i2c/sim/work/i2c_master_top/_primary.vhd
i2c/sim/work/i2c_slave_model/verilog.asm
i2c/sim/work/i2c_slave_model/_primary.dat
i2c/sim/work/i2c_slave_model/_primary.vhd
i2c/sim/work/maxii_and1/verilog.asm
i2c/sim/work/maxii_and1/_primary.dat
i2c/sim/work/maxii_and1/_primary.vhd
i2c/sim/work/maxii_and16/verilog.asm
i2c/sim/work/maxii_and16/_primary.dat
i2c/sim/work/maxii_and16/_primary.vhd
i2c/sim/work/maxii_asynch_lcell/verilog.asm
i2c/sim/work/maxii_asynch_lcell/_primary.dat
i2c/sim/work/maxii_asynch_lcell/_primary.vhd
i2c/sim/work/maxii_b17mux21/verilog.asm
i2c/sim/work/maxii_b17mux21/_primary.dat
i2c/sim/work/maxii_b17mux21/_primary.vhd
i2c/sim/work/maxii_b5mux21/verilog.asm
i2c/sim/work/maxii_b5mux21/_primary.dat
i2c/sim/work/maxii_b5mux21/_primary.vhd
i2c/sim/work/maxii_bmux21/verilog.asm
i2c/sim/work/maxii_bmux21/_primary.dat
i2c/sim/work/maxii_bmux21/_primary.vhd
i2c/sim/work/maxii_dffe/verilog.asm
i2c/sim/work/maxii_dffe/_primary.dat
i2c/sim/work/maxii_dffe/_primary.vhd
i2c/sim/work/maxii_io/verilog.asm
i2c/sim/work/maxii_io/_primary.dat
i2c/sim/work/maxii_io/_primary.vhd
i2c/sim/work/maxii_latch/verilog.asm
i2c/sim/work/maxii_latch/_primary.dat
i2c/sim/work/maxii_latch/_primary.vhd
i2c/sim/work/maxii_lcell/verilog.asm
i2c/sim/work/maxii_lcell/_primary.dat
i2c/sim/work/maxii_lcell/_primary.vhd
i2c/sim/work/maxii_lcell_register/verilog.asm
i2c/sim/work/maxii_lcell_register/_primary.dat
i2c/sim/work/maxii_lcell_register/_primary.vhd
i2c/sim/work/maxii_mux21/verilog.asm
i2c/sim/work/maxii_mux21/_primary.dat
i2c/sim/work/maxii_mux21/_primary.vhd
i2c/sim/work/maxii_mux41/verilog.asm
i2c/sim/work/maxii_mux41/_primary.dat
i2c/sim/work/maxii_mux41/_primary.vhd
i2c/sim/work/maxii_nmux21/verilog.asm
i2c/sim/work/maxii_nmux21/_primary.dat
i2c/sim/work/maxii_nmux21/_primary.vhd
i2c/sim/work/maxii_routing_wire/verilog.asm
i2c/sim/work/maxii_routing_wire/_primary.dat
i2c/sim/work/maxii_routing_wire/_primary.vhd
i2c/sim/work/maxii_ufm/verilog.asm
i2c/sim/work/maxii_ufm/_primary.dat
i2c/sim/work/maxii_ufm/_primary.vhd
i2c/sim/work/tst_bench_top/verilog.asm
i2c/sim/work/tst_bench_top/_primary.dat
i2c/sim/work/tst_bench_top/_primary.vhd
i2c/sim/work/wb_master_model/verilog.asm
i2c/sim/work/wb_master_model/_primary.dat
i2c/sim/work/wb_master_model/_primary.vhd
i2c/sim/work/_info
i2c/software/CVS/Entries
i2c/software/CVS/R
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