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文件名称:LatticeMico8_v3_0_Verilog

  • 所属分类：
    VHDL-FPGA-Verilog
  • 标签属性：
    [VHDL] [源码]
  • 上传时间：
    2012-11-16
  • 文件大小：
    1.1mb
  • 已下载：
    0次
  • 提 供 者：
    郭****
  • 相关连接：
    无
  • 下载说明：
    别用迅雷下载，失败请重下，重下不扣分！
修正介绍说明

介绍说明－－下载内容来自于网络，使用问题请自行百度

The LatticeMico8™ is an 8-bit microcontroller optimized for Field Programmable Gate Arrays (FPGAs) and Crossover Programmable Logic Device architectures from Lattice.

Combining a full 18-bit wide instruction set with 16 or 32 General Purpose registers, the LatticeMico8 is a flexible Verilog and VHDL reference design suitable for a wide variety of markets, including communications, consumer, computer, medical, industrial, and automotive.

The core consumes minimal device resources, less than 200 Look Up Tables (LUTs) in the smallest configuration, while maintaining a broad feature set.-The LatticeMico8™　is an 8-bit microcontroller optimized for Field Programmable Gate Arrays (FPGAs) and Crossover Programmable Logic Device architectures from Lattice.

Combining a full 18-bit wide instruction set with 16 or 32 General Purpose registers, the LatticeMico8 is a flexible Verilog and VHDL reference design suitable for a wide variety of markets, including communications, consumer, computer, medical, industrial, and automotive.

The core consumes minimal device resources, less than 200 Look Up Tables (LUTs) in the smallest configuration, while maintaining a broad feature set.
相关搜索： lm75 verilog .v lattice lattice design LatticeMic IBPU latti LatticeMico8_v3_0_Verilog

(系统自动生成,下载前可以参看下载内容)

下载文件列表

LatticeMico8_V3_0_Verilog/models/
LatticeMico8_V3_0_Verilog/models/pmi/
LatticeMico8_V3_0_Verilog/models/pmi/pmi_add.v
LatticeMico8_V3_0_Verilog/models/pmi/pmi_addsub.v
LatticeMico8_V3_0_Verilog/models/pmi/pmi_complex_mult.v
LatticeMico8_V3_0_Verilog/models/pmi/pmi_constant_mult.v
LatticeMico8_V3_0_Verilog/models/pmi/pmi_counter.v
LatticeMico8_V3_0_Verilog/models/pmi/pmi_def.v
LatticeMico8_V3_0_Verilog/models/pmi/pmi_distributed_dpram.v
LatticeMico8_V3_0_Verilog/models/pmi/pmi_distributed_rom.v
LatticeMico8_V3_0_Verilog/models/pmi/pmi_distributed_shift_reg.v
LatticeMico8_V3_0_Verilog/models/pmi/pmi_distributed_spram.v
LatticeMico8_V3_0_Verilog/models/pmi/pmi_dsp_mac.v
LatticeMico8_V3_0_Verilog/models/pmi/pmi_dsp_mult.v
LatticeMico8_V3_0_Verilog/models/pmi/pmi_dsp_multaddsub.v
LatticeMico8_V3_0_Verilog/models/pmi/pmi_dsp_multaddsubsum.v
LatticeMico8_V3_0_Verilog/models/pmi/pmi_fifo.v
LatticeMico8_V3_0_Verilog/models/pmi/pmi_fifo_dc.v
LatticeMico8_V3_0_Verilog/models/pmi/pmi_mac.v
LatticeMico8_V3_0_Verilog/models/pmi/pmi_mult.v
LatticeMico8_V3_0_Verilog/models/pmi/pmi_multaddsub.v
LatticeMico8_V3_0_Verilog/models/pmi/pmi_multaddsubsum.v
LatticeMico8_V3_0_Verilog/models/pmi/pmi_pll.v
LatticeMico8_V3_0_Verilog/models/pmi/pmi_ram_dp.v
LatticeMico8_V3_0_Verilog/models/pmi/pmi_ram_dp_true.v
LatticeMico8_V3_0_Verilog/models/pmi/pmi_ram_dq.v
LatticeMico8_V3_0_Verilog/models/pmi/pmi_rom.v
LatticeMico8_V3_0_Verilog/models/pmi/pmi_sub.v
LatticeMico8_V3_0_Verilog/models/xo/
LatticeMico8_V3_0_Verilog/models/xo/sim/
LatticeMico8_V3_0_Verilog/models/xo/sim/AGEB2.v
LatticeMico8_V3_0_Verilog/models/xo/sim/ALEB2.v
LatticeMico8_V3_0_Verilog/models/xo/sim/AND2.v
LatticeMico8_V3_0_Verilog/models/xo/sim/AND3.v
LatticeMico8_V3_0_Verilog/models/xo/sim/AND4.v
LatticeMico8_V3_0_Verilog/models/xo/sim/AND5.v
LatticeMico8_V3_0_Verilog/models/xo/sim/ANEB2.v
LatticeMico8_V3_0_Verilog/models/xo/sim/BB.v
LatticeMico8_V3_0_Verilog/models/xo/sim/BBPD.v
LatticeMico8_V3_0_Verilog/models/xo/sim/BBPU.v
LatticeMico8_V3_0_Verilog/models/xo/sim/BBW.v
LatticeMico8_V3_0_Verilog/models/xo/sim/BUFBA.v
LatticeMico8_V3_0_Verilog/models/xo/sim/CB2.v
LatticeMico8_V3_0_Verilog/models/xo/sim/CCU2.v
LatticeMico8_V3_0_Verilog/models/xo/sim/CD2.v
LatticeMico8_V3_0_Verilog/models/xo/sim/CU2.v
LatticeMico8_V3_0_Verilog/models/xo/sim/DP8KB.v
LatticeMico8_V3_0_Verilog/models/xo/sim/DPR16X2B.v
LatticeMico8_V3_0_Verilog/models/xo/sim/EHXPLLC.v
LatticeMico8_V3_0_Verilog/models/xo/sim/FADD2.v
LatticeMico8_V3_0_Verilog/models/xo/sim/FADSU2.v
LatticeMico8_V3_0_Verilog/models/xo/sim/FD1P3AX.v
LatticeMico8_V3_0_Verilog/models/xo/sim/FD1P3AY.v
LatticeMico8_V3_0_Verilog/models/xo/sim/FD1P3BX.v
LatticeMico8_V3_0_Verilog/models/xo/sim/FD1P3DX.v
LatticeMico8_V3_0_Verilog/models/xo/sim/FD1P3IX.v
LatticeMico8_V3_0_Verilog/models/xo/sim/FD1P3JX.v
LatticeMico8_V3_0_Verilog/models/xo/sim/FD1S1A.v
LatticeMico8_V3_0_Verilog/models/xo/sim/FD1S1AY.v
LatticeMico8_V3_0_Verilog/models/xo/sim/FD1S1B.v
LatticeMico8_V3_0_Verilog/models/xo/sim/FD1S1D.v
LatticeMico8_V3_0_Verilog/models/xo/sim/FD1S1I.v
LatticeMico8_V3_0_Verilog/models/xo/sim/FD1S1J.v
LatticeMico8_V3_0_Verilog/models/xo/sim/FD1S3AX.v
LatticeMico8_V3_0_Verilog/models/xo/sim/FD1S3AY.v
LatticeMico8_V3_0_Verilog/models/xo/sim/FD1S3BX.v
LatticeMico8_V3_0_Verilog/models/xo/sim/FD1S3DX.v
LatticeMico8_V3_0_Verilog/models/xo/sim/FD1S3IX.v
LatticeMico8_V3_0_Verilog/models/xo/sim/FD1S3JX.v
LatticeMico8_V3_0_Verilog/models/xo/sim/FIFO8KA.v
LatticeMico8_V3_0_Verilog/models/xo/sim/FL1P3AY.v
LatticeMico8_V3_0_Verilog/models/xo/sim/FL1P3AY_FUNC.v
LatticeMico8_V3_0_Verilog/models/xo/sim/FL1P3AZ.v
LatticeMico8_V3_0_Verilog/models/xo/sim/FL1P3AZ_FUNC.v
LatticeMico8_V3_0_Verilog/models/xo/sim/FL1P3BX.v
LatticeMico8_V3_0_Verilog/models/xo/sim/FL1P3BX_FUNC.v
LatticeMico8_V3_0_Verilog/models/xo/sim/FL1P3DX.v
LatticeMico8_V3_0_Verilog/models/xo/sim/FL1P3DX_FUNC.v
LatticeMico8_V3_0_Verilog/models/xo/sim/FL1P3IY.v
LatticeMico8_V3_0_Verilog/models/xo/sim/FL1P3IY_FUNC.v
LatticeMico8_V3_0_Verilog/models/xo/sim/FL1P3JY.v
LatticeMico8_V3_0_Verilog/models/xo/sim/FL1P3JY_FUNC.v
LatticeMico8_V3_0_Verilog/models/xo/sim/FL1S1A.v
LatticeMico8_V3_0_Verilog/models/xo/sim/FL1S1AY.v
LatticeMico8_V3_0_Verilog/models/xo/sim/FL1S1B.v
LatticeMico8_V3_0_Verilog/models/xo/sim/FL1S1D.v
LatticeMico8_V3_0_Verilog/models/xo/sim/FL1S1I.v
LatticeMico8_V3_0_Verilog/models/xo/sim/FL1S1J.v
LatticeMico8_V3_0_Verilog/models/xo/sim/FL1S3AX.v
LatticeMico8_V3_0_Verilog/models/xo/sim/FL1S3AY.v
LatticeMico8_V3_0_Verilog/models/xo/sim/FSUB2.v
LatticeMico8_V3_0_Verilog/models/xo/sim/GSR.v
LatticeMico8_V3_0_Verilog/models/xo/sim/IB.v
LatticeMico8_V3_0_Verilog/models/xo/sim/IBPD.v
LatticeMico8_V3_0_Verilog/models/xo/sim/IBPU.v
LatticeMico8_V3_0_Verilog/models/xo/sim/ILVDS.v
LatticeMico8_V3_0_Verilog/models/xo/sim/INV.v
LatticeMico8_V3_0_Verilog/models/xo/sim/JTAGD.v
LatticeMico8_V3_0_Verilog/models/xo/sim/L6MUX21.v
LatticeMico8_V3_0_Verilog/models/xo/sim/LB2P3AX.v
LatticeMico8_V3_0_Verilog/models/xo/sim/LB2P3AY.v
LatticeMico8_V3_0_Verilog/models/xo/sim/LB2P3BX.v
LatticeMico8_V3_0_Verilog/models/xo/sim/LB2P3DX.v
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