文件名称:DE2_70_TV
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- 上传时间：2012-11-16
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文件大小：164.93kb
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This design converts DVD video into a format suitable for display on a CRT/LCD monitor. A DVD video source, such as a DVD player, should be connected to the VIDEO IN port on the DE2-70 board. A CRT/LCD monitor should be connected to the VGA port. The DVD video should be displayed on the monitor.
Initially, the video may be shifted vertically press KEY0 to force the design to resynchronize.--------------------Verilog----------------
This design converts DVD video into a format suitable for display on a CRT/LCD monitor. A DVD video source, such as a DVD player, should be connected to the VIDEO IN port on the DE2-70 board. A CRT/LCD monitor should be connected to the VGA port. The DVD video should be displayed on the monitor.
Initially, the video may be shifted vertically press KEY0 to force the design to resynchronize.
This design converts DVD video into a format suitable for display on a CRT/LCD monitor. A DVD video source, such as a DVD player, should be connected to the VIDEO IN port on the DE2-70 board. A CRT/LCD monitor should be connected to the VGA port. The DVD video should be displayed on the monitor.
Initially, the video may be shifted vertically press KEY0 to force the design to resynchronize.--------------------Verilog----------------
This design converts DVD video into a format suitable for display on a CRT/LCD monitor. A DVD video source, such as a DVD player, should be connected to the VIDEO IN port on the DE2-70 board. A CRT/LCD monitor should be connected to the VGA port. The DVD video should be displayed on the monitor.
Initially, the video may be shifted vertically press KEY0 to force the design to resynchronize.
相关搜索： DE2_70_TV
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下载文件列表
DE2_70_TV/AUDIO_DAC.v
DE2_70_TV/db/DE2_70_TV.db_info
DE2_70_TV/db/DE2_70_TV.eco.cdb
DE2_70_TV/db/DE2_70_TV.sld_design_entry.sci
DE2_70_TV/db
DE2_70_TV/DE2_70_TV.pof
DE2_70_TV/DE2_70_TV.qpf
DE2_70_TV/DE2_70_TV.qsf
DE2_70_TV/DE2_70_TV.qws
DE2_70_TV/DE2_70_TV.sof
DE2_70_TV/DE2_70_TV.v
DE2_70_TV/DE2_70_TV_assignment_defaults.qdf
DE2_70_TV/DIV.v
DE2_70_TV/I2C_AV_Config.v
DE2_70_TV/I2C_Controller.v
DE2_70_TV/ITU_656_Decoder.v
DE2_70_TV/Line_Buffer.v
DE2_70_TV/MAC_3.v
DE2_70_TV/PLL.v
DE2_70_TV/README.txt
DE2_70_TV/Reset_Delay.v
DE2_70_TV/Sdram_Control_4Port/command.v
DE2_70_TV/Sdram_Control_4Port/control_interface.v
DE2_70_TV/Sdram_Control_4Port/Sdram_Control_4Port.v
DE2_70_TV/Sdram_Control_4Port/Sdram_Params.h
DE2_70_TV/Sdram_Control_4Port/Sdram_PLL.bsf
DE2_70_TV/Sdram_Control_4Port/Sdram_PLL.ppf
DE2_70_TV/Sdram_Control_4Port/Sdram_PLL.v
DE2_70_TV/Sdram_Control_4Port/Sdram_RD_FIFO.v
DE2_70_TV/Sdram_Control_4Port/Sdram_WR_FIFO.v
DE2_70_TV/Sdram_Control_4Port/sdr_data_path.v
DE2_70_TV/Sdram_Control_4Port
DE2_70_TV/SEG7_LUT.v
DE2_70_TV/SEG7_LUT_8.v
DE2_70_TV/TD_Detect.v
DE2_70_TV/TP_RAM.v
DE2_70_TV/VGA_Ctrl.v
DE2_70_TV/YCbCr2RGB.v
DE2_70_TV/YUV422_to_444.v
DE2_70_TV
DE2_70_TV/db/DE2_70_TV.db_info
DE2_70_TV/db/DE2_70_TV.eco.cdb
DE2_70_TV/db/DE2_70_TV.sld_design_entry.sci
DE2_70_TV/db
DE2_70_TV/DE2_70_TV.pof
DE2_70_TV/DE2_70_TV.qpf
DE2_70_TV/DE2_70_TV.qsf
DE2_70_TV/DE2_70_TV.qws
DE2_70_TV/DE2_70_TV.sof
DE2_70_TV/DE2_70_TV.v
DE2_70_TV/DE2_70_TV_assignment_defaults.qdf
DE2_70_TV/DIV.v
DE2_70_TV/I2C_AV_Config.v
DE2_70_TV/I2C_Controller.v
DE2_70_TV/ITU_656_Decoder.v
DE2_70_TV/Line_Buffer.v
DE2_70_TV/MAC_3.v
DE2_70_TV/PLL.v
DE2_70_TV/README.txt
DE2_70_TV/Reset_Delay.v
DE2_70_TV/Sdram_Control_4Port/command.v
DE2_70_TV/Sdram_Control_4Port/control_interface.v
DE2_70_TV/Sdram_Control_4Port/Sdram_Control_4Port.v
DE2_70_TV/Sdram_Control_4Port/Sdram_Params.h
DE2_70_TV/Sdram_Control_4Port/Sdram_PLL.bsf
DE2_70_TV/Sdram_Control_4Port/Sdram_PLL.ppf
DE2_70_TV/Sdram_Control_4Port/Sdram_PLL.v
DE2_70_TV/Sdram_Control_4Port/Sdram_RD_FIFO.v
DE2_70_TV/Sdram_Control_4Port/Sdram_WR_FIFO.v
DE2_70_TV/Sdram_Control_4Port/sdr_data_path.v
DE2_70_TV/Sdram_Control_4Port
DE2_70_TV/SEG7_LUT.v
DE2_70_TV/SEG7_LUT_8.v
DE2_70_TV/TD_Detect.v
DE2_70_TV/TP_RAM.v
DE2_70_TV/VGA_Ctrl.v
DE2_70_TV/YCbCr2RGB.v
DE2_70_TV/YUV422_to_444.v
DE2_70_TV
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