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文件名称:CoreI2C

  • 所属分类：
    VHDL-FPGA-Verilog
  • 标签属性：
    [VHDL] [源码]
  • 上传时间：
    2012-11-16
  • 文件大小：
    4.85mb
  • 已下载：
    0次
  • 提 供 者：
    王****
  • 相关连接：
    无
  • 下载说明：
    别用迅雷下载，失败请重下，重下不扣分！
修正介绍说明

介绍说明－－下载内容来自于网络，使用问题请自行百度

CoreI2C实验的源代码-Experimental CoreI2C source code. . . . . . . . . . .
相关搜索： corei

(系统自动生成,下载前可以参看下载内容)

下载文件列表

CoreI2C实验/Project/CoreI2C/constraint/i2c_top.pdc
CoreI2C实验/Project/CoreI2C/CORE.prj
CoreI2C实验/Project/CoreI2C/designer/impl1/designer.log
CoreI2C实验/Project/CoreI2C/designer/impl1/designer_genhdl.log
CoreI2C实验/Project/CoreI2C/designer/impl1/top.adb
CoreI2C实验/Project/CoreI2C/designer/impl1/top.dtf/verify.log
CoreI2C实验/Project/CoreI2C/designer/impl1/top.ide_des
CoreI2C实验/Project/CoreI2C/designer/impl1/top.pdb
CoreI2C实验/Project/CoreI2C/designer/impl1/top.pdb.depends
CoreI2C实验/Project/CoreI2C/designer/impl1/top.stp
CoreI2C实验/Project/CoreI2C/designer/impl1/top.tcl
CoreI2C实验/Project/CoreI2C/designer/impl1/top_ba.sdf
CoreI2C实验/Project/CoreI2C/designer/impl1/top_ba.v
CoreI2C实验/Project/CoreI2C/hdl/core8051_oci0_withoutio_pa3.v
CoreI2C实验/Project/CoreI2C/hdl/hdlsynchk.tcl
CoreI2C实验/Project/CoreI2C/hdl/i2c_master_bit_ctrl.v
CoreI2C实验/Project/CoreI2C/hdl/i2c_master_byte_ctrl.v
CoreI2C实验/Project/CoreI2C/hdl/i2c_master_defines.v
CoreI2C实验/Project/CoreI2C/hdl/i2c_master_top.v
CoreI2C实验/Project/CoreI2C/hdl/rec.v
CoreI2C实验/Project/CoreI2C/hdl/timescale.v
CoreI2C实验/Project/CoreI2C/hdl/top.v
CoreI2C实验/Project/CoreI2C/hdl/user_core8051.v
CoreI2C实验/Project/CoreI2C/simulation/meminit.dat
CoreI2C实验/Project/CoreI2C/simulation/modelsim.ini
CoreI2C实验/Project/CoreI2C/simulation/modelsim.ini.sav
CoreI2C实验/Project/CoreI2C/simulation/RAM256X8_R0C0.mem
CoreI2C实验/Project/CoreI2C/simulation/RAM2KX8_R0C0.mem
CoreI2C实验/Project/CoreI2C/simulation/RAM2KX8_R0C1.mem
CoreI2C实验/Project/CoreI2C/simulation/RAM2KX8_R0C2.mem
CoreI2C实验/Project/CoreI2C/simulation/RAM2KX8_R0C3.mem
CoreI2C实验/Project/CoreI2C/smartgen/pll18m/pll18m.cxf
CoreI2C实验/Project/CoreI2C/smartgen/pll18m/pll18m.gen
CoreI2C实验/Project/CoreI2C/smartgen/pll18m/pll18m.log
CoreI2C实验/Project/CoreI2C/smartgen/pll18m/pll18m.v
CoreI2C实验/Project/CoreI2C/smartgen/pll18m_work.ixf
CoreI2C实验/Project/CoreI2C/smartgen/RAM256X8/RAM256X8.cxf
CoreI2C实验/Project/CoreI2C/smartgen/RAM256X8/RAM256X8.gen
CoreI2C实验/Project/CoreI2C/smartgen/RAM256X8/RAM256X8.log
CoreI2C实验/Project/CoreI2C/smartgen/RAM256X8/RAM256X8.shx
CoreI2C实验/Project/CoreI2C/smartgen/RAM256X8/RAM256X8.v
CoreI2C实验/Project/CoreI2C/smartgen/RAM256X8/RAM256X8_R0C0.mem
CoreI2C实验/Project/CoreI2C/smartgen/RAM256X8_work.ixf
CoreI2C实验/Project/CoreI2C/smartgen/RAM2KX8/RAM2KX8.cxf
CoreI2C实验/Project/CoreI2C/smartgen/RAM2KX8/RAM2KX8.gen
CoreI2C实验/Project/CoreI2C/smartgen/RAM2KX8/RAM2KX8.log
CoreI2C实验/Project/CoreI2C/smartgen/RAM2KX8/RAM2KX8.shx
CoreI2C实验/Project/CoreI2C/smartgen/RAM2KX8/RAM2KX8.v
CoreI2C实验/Project/CoreI2C/smartgen/RAM2KX8/RAM2KX8_R0C0.mem
CoreI2C实验/Project/CoreI2C/smartgen/RAM2KX8/RAM2KX8_R0C1.mem
CoreI2C实验/Project/CoreI2C/smartgen/RAM2KX8/RAM2KX8_R0C2.mem
CoreI2C实验/Project/CoreI2C/smartgen/RAM2KX8/RAM2KX8_R0C3.mem
CoreI2C实验/Project/CoreI2C/smartgen/RAM2KX8_work.ixf
CoreI2C实验/Project/CoreI2C/smartgen/smartgen.aws
CoreI2C实验/Project/CoreI2C/synthesis/.recordref
CoreI2C实验/Project/CoreI2C/synthesis/backup/top.srr
CoreI2C实验/Project/CoreI2C/synthesis/run_options.txt
CoreI2C实验/Project/CoreI2C/synthesis/stdout.log
CoreI2C实验/Project/CoreI2C/synthesis/syntmp/top.msg
CoreI2C实验/Project/CoreI2C/synthesis/syntmp/top.plg
CoreI2C实验/Project/CoreI2C/synthesis/top.areasrr
CoreI2C实验/Project/CoreI2C/synthesis/top.edn
CoreI2C实验/Project/CoreI2C/synthesis/top.map
CoreI2C实验/Project/CoreI2C/synthesis/top.sdf
CoreI2C实验/Project/CoreI2C/synthesis/top.srd
CoreI2C实验/Project/CoreI2C/synthesis/top.srm
CoreI2C实验/Project/CoreI2C/synthesis/top.srr
CoreI2C实验/Project/CoreI2C/synthesis/top.srs
CoreI2C实验/Project/CoreI2C/synthesis/top.tlg
CoreI2C实验/Project/CoreI2C/synthesis/top_drc.rpt
CoreI2C实验/Project/CoreI2C/synthesis/top_sdc.sdc
CoreI2C实验/Project/CoreI2C/synthesis/top_syn.prd
CoreI2C实验/Project/CoreI2C/synthesis/top_syn.prj
CoreI2C实验/Project/CoreI2C/synthesis/traplog.tlg
CoreI2C实验/Project/CoreI2C/viewdraw/vf/project.lst
CoreI2C实验/Project/CoreI2C/viewdraw/viewdraw.ini
CoreI2C实验/Source/core8051_oci0_withoutio_pa3.v
CoreI2C实验/Source/i2c_master_bit_ctrl.v
CoreI2C实验/Source/i2c_master_byte_ctrl.v
CoreI2C实验/Source/i2c_master_defines.v
CoreI2C实验/Source/i2c_master_top.v
CoreI2C实验/Source/rec.v
CoreI2C实验/Source/timescale.v
CoreI2C实验/Source/top.v
CoreI2C实验/Source/user_core8051.v
CoreI2C实验/Project/CoreI2C/designer/impl1/simulation
CoreI2C实验/Project/CoreI2C/designer/impl1/top.dtf
CoreI2C实验/Project/CoreI2C/designer/impl1
CoreI2C实验/Project/CoreI2C/smartgen/pll18m
CoreI2C实验/Project/CoreI2C/smartgen/RAM256X8
CoreI2C实验/Project/CoreI2C/smartgen/RAM2KX8
CoreI2C实验/Project/CoreI2C/synthesis/backup
CoreI2C实验/Project/CoreI2C/synthesis/syntmp
CoreI2C实验/Project/CoreI2C/viewdraw/sch
CoreI2C实验/Project/CoreI2C/viewdraw/sym
CoreI2C实验/Project/CoreI2C/viewdraw/vf
CoreI2C实验/Project/CoreI2C/viewdraw/wir
CoreI2C实验/Project/CoreI2C/component
CoreI2C实验/Project/CoreI2C/constraint
CoreI2C实验/Project/CoreI2C/coreconsole
CoreI2C实验/Project/CoreI2C/designer
CoreI2C实验/Project/CoreI2C/hdl
CoreI2C实验/Project/CoreI2C/phy_synthesis
CoreI2C实验/Project/CoreI2C/simulation
CoreI2C实验/Project/CoreI2C/smartgen
CoreI2C实验/Project/CoreI2C/stimulus
CoreI2C实验/Project/CoreI2C/synthesis
CoreI2C实验/Project/CoreI2C/viewdraw
CoreI2C实验/Project/CoreI2C
CoreI2C实验/Proje

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