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文件名称:tester

  • 所属分类:
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  • 上传时间:
    2012-11-16
  • 文件大小:
    779.53kb
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    0次
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通过时钟计数实现是鲜红分配,复位封锁,分频等-时钟计数,复位封锁
(系统自动生成,下载前可以参看下载内容)

下载文件列表

testerFPGA/testerFPGA/constraint/pp.gcf
testerFPGA/testerFPGA/constraint/top.gcf
testerFPGA/testerFPGA/constraint/top.gcf.bak
testerFPGA/testerFPGA/coreconsole/ram/ram.cci
testerFPGA/testerFPGA/designer/impl1/designer.log
testerFPGA/testerFPGA/designer/impl1/hdlc_with_sram-am.sdf
testerFPGA/testerFPGA/designer/impl1/hdlc_with_sram.adb
testerFPGA/testerFPGA/designer/impl1/hdlc_with_sram.adl
testerFPGA/testerFPGA/designer/impl1/hdlc_with_sram.dtf/bitgen.log
testerFPGA/testerFPGA/designer/impl1/hdlc_with_sram.dtf/floorplan.gcf
testerFPGA/testerFPGA/designer/impl1/hdlc_with_sram.dtf/floorplan.gcf.old
testerFPGA/testerFPGA/designer/impl1/hdlc_with_sram.dtf/import.log
testerFPGA/testerFPGA/designer/impl1/hdlc_with_sram.dtf/last_placement.gcf
testerFPGA/testerFPGA/designer/impl1/hdlc_with_sram.dtf/masks
testerFPGA/testerFPGA/designer/impl1/hdlc_with_sram.dtf/masks.final
testerFPGA/testerFPGA/designer/impl1/hdlc_with_sram.dtf/master-des.gcf
testerFPGA/testerFPGA/designer/impl1/hdlc_with_sram.dtf/master.gcf
testerFPGA/testerFPGA/designer/impl1/hdlc_with_sram.dtf/mem_plmt.gcf
testerFPGA/testerFPGA/designer/impl1/hdlc_with_sram.dtf/place.log
testerFPGA/testerFPGA/designer/impl1/hdlc_with_sram.dtf/route.log
testerFPGA/testerFPGA/designer/impl1/hdlc_with_sram.dtf/time.log
testerFPGA/testerFPGA/designer/impl1/hdlc_with_sram.ide_des
testerFPGA/testerFPGA/designer/impl1/hdlc_with_sram.stp
testerFPGA/testerFPGA/designer/impl1/hdlc_with_sram.tcl
testerFPGA/testerFPGA/designer/impl1/test.adb
testerFPGA/testerFPGA/designer/impl1/test.adl
testerFPGA/testerFPGA/designer/impl1/test.dtf/import.log
testerFPGA/testerFPGA/designer/impl1/test.dtf/master-des.gcf
testerFPGA/testerFPGA/designer/impl1/test.dtf/master.gcf
testerFPGA/testerFPGA/designer/impl1/test.ide_des
testerFPGA/testerFPGA/designer/impl1/test.tcl
testerFPGA/testerFPGA/designer/impl1/top-am.sdf
testerFPGA/testerFPGA/designer/impl1/top.adb
testerFPGA/testerFPGA/designer/impl1/top.adl
testerFPGA/testerFPGA/designer/impl1/top.dtf/bitgen.log
testerFPGA/testerFPGA/designer/impl1/top.dtf/floorplan-des.gcf
testerFPGA/testerFPGA/designer/impl1/top.dtf/floorplan.gcf
testerFPGA/testerFPGA/designer/impl1/top.dtf/floorplan.gcf.old
testerFPGA/testerFPGA/designer/impl1/top.dtf/import.log
testerFPGA/testerFPGA/designer/impl1/top.dtf/initial_placement.gcf
testerFPGA/testerFPGA/designer/impl1/top.dtf/last_placement.gcf
testerFPGA/testerFPGA/designer/impl1/top.dtf/masks
testerFPGA/testerFPGA/designer/impl1/top.dtf/masks.final
testerFPGA/testerFPGA/designer/impl1/top.dtf/master-des.gcf
testerFPGA/testerFPGA/designer/impl1/top.dtf/master.gcf
testerFPGA/testerFPGA/designer/impl1/top.dtf/mem_plmt.gcf
testerFPGA/testerFPGA/designer/impl1/top.dtf/place.log
testerFPGA/testerFPGA/designer/impl1/top.dtf/route.log
testerFPGA/testerFPGA/designer/impl1/top.dtf/time.log
testerFPGA/testerFPGA/designer/impl1/top.ide_des
testerFPGA/testerFPGA/designer/impl1/top.lok
testerFPGA/testerFPGA/designer/impl1/top.stp
testerFPGA/testerFPGA/designer/impl1/top.tcl
testerFPGA/testerFPGA/designer/impl1/top_1.adb
testerFPGA/testerFPGA/designer/impl1/top_1.dtf/import.log
testerFPGA/testerFPGA/designer/impl1/top_1.dtf/master-des.gcf
testerFPGA/testerFPGA/designer/impl1/top_1.dtf/master.gcf
testerFPGA/testerFPGA/designer/impl1/top_1.ide_des
testerFPGA/testerFPGA/designer/impl1/top_2.adb
testerFPGA/testerFPGA/designer/impl1/top_2.dtf/import.log
testerFPGA/testerFPGA/designer/impl1/top_2.dtf/master-des.gcf
testerFPGA/testerFPGA/designer/impl1/top_2.dtf/master.gcf
testerFPGA/testerFPGA/designer/impl1/top_2.ide_des
testerFPGA/testerFPGA/designer/impl1/top_fp/projectData/top.stp
testerFPGA/testerFPGA/designer/impl1/top_fp/top.log
testerFPGA/testerFPGA/designer/impl1/top_fp/top.pro
testerFPGA/testerFPGA/hdl/ackreset.v
testerFPGA/testerFPGA/hdl/adcon.v
testerFPGA/testerFPGA/hdl/clk_100k.v
testerFPGA/testerFPGA/hdl/count.v
testerFPGA/testerFPGA/hdl/count5ms.v
testerFPGA/testerFPGA/hdl/countkg.v
testerFPGA/testerFPGA/hdl/gen_low_pulse.v
testerFPGA/testerFPGA/hdl/gen_low_pulsetl.v
testerFPGA/testerFPGA/hdl/gen_tl.v
testerFPGA/testerFPGA/hdl/koutshibie.v
testerFPGA/testerFPGA/hdl/k_inxx.v
testerFPGA/testerFPGA/hdl/muxswich.v
testerFPGA/testerFPGA/hdl/pp.v
testerFPGA/testerFPGA/hdl/prgctl.v
testerFPGA/testerFPGA/hdl/resetfsuo.v
testerFPGA/testerFPGA/hdl/rstnx.v
testerFPGA/testerFPGA/hdl/test.v
testerFPGA/testerFPGA/hdl/prgctl_chang.v
testerFPGA/testerFPGA/hdl/mdc_in.txt
testerFPGA/testerFPGA/simulation/dualram256_M0.mem
testerFPGA/testerFPGA/simulation/modelsim.ini
testerFPGA/testerFPGA/simulation/modelsim.ini.sav
testerFPGA/testerFPGA/simulation/sram256x8aa_M0.mem
testerFPGA/testerFPGA/smartgen/clk_50m/clk_50m.cxf
testerFPGA/testerFPGA/smartgen/clk_50m/clk_50m.gen
testerFPGA/testerFPGA/smartgen/clk_50m/clk_50m.log
testerFPGA/testerFPGA/smartgen/clk_50m/clk_50m.v
testerFPGA/testerFPGA/smartgen/clk_50m_work.ixf
testerFPGA/testerFPGA/smartgen/dualram256/dualram256.cxf
testerFPGA/testerFPGA/smartgen/dualram256/dualram256.gen
testerFPGA/testerFPGA/smartgen/dualram256/dualram256.log
testerFPGA/testerFPGA/smartgen/dualram256/dualram256.v
testerFPGA/testerF

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