要求：并行输入1 byte，串行输出，无数据时输出高电平，输出格式1100+8bit+奇偶校验+0011（停止位）串行输入，并行输出，检测是否奇偶校验错误，是否有帧传输错误传输每bit数据占16个clock周期

-Requirements: parallel importation of 1 byte, serial output, no data output high, output format 1100+8 bit+ parity+0011 (stop bit) serial input, parallel output, detect the parity error, whether there is transmission frame for each bit of data transmission errors accounted for 16 clock cycles