文件名称:74HC194
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- 上传时间:2012-11-16
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文件大小:1.11mb
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74ls194 基于verilog语言的实现 -Verilog language 74ls194 based on the realization of
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下载文件列表
74hc194.pdf
74hc194/
74hc194/74hc194.prj
74hc194/component/
74hc194/constraint/
74hc194/coreconsole/
74hc194/designer/
74hc194/designer/impl1/
74hc194/designer/impl1/designer.log
74hc194/designer/impl1/shift4.adb
74hc194/designer/impl1/shift4.dtf/
74hc194/designer/impl1/shift4.dtf/verify.log
74hc194/designer/impl1/shift4.ide_des
74hc194/designer/impl1/shift4.pdb
74hc194/designer/impl1/shift4.pdb.depends
74hc194/designer/impl1/shift4.tcl
74hc194/designer/impl1/shift4_fp/
74hc194/designer/impl1/shift4_fp/$$FlashPro_07294.L$$
74hc194/designer/impl1/shift4_fp/projectData/
74hc194/designer/impl1/shift4_fp/projectData/shift4.pdb
74hc194/designer/impl1/shift4_fp/shift4.log
74hc194/designer/impl1/shift4_fp/shift4.pro
74hc194/designer/impl1/simulation/
74hc194/hdl/
74hc194/hdl/74hc194.v
74hc194/phy_synthesis/
74hc194/simulation/
74hc194/simulation/modelsim.ini
74hc194/simulation/modelsim.ini.sav
74hc194/simulation/modelsim.log
74hc194/simulation/presynth/
74hc194/simulation/presynth/shift4/
74hc194/simulation/presynth/shift4/verilog.psm
74hc194/simulation/presynth/shift4/_primary.dat
74hc194/simulation/presynth/shift4/_primary.dbs
74hc194/simulation/presynth/shift4/_primary.vhd
74hc194/simulation/presynth/testbench/
74hc194/simulation/presynth/testbench/verilog.psm
74hc194/simulation/presynth/testbench/_primary.dat
74hc194/simulation/presynth/testbench/_primary.dbs
74hc194/simulation/presynth/testbench/_primary.vhd
74hc194/simulation/presynth/_info
74hc194/simulation/presynth/_temp/
74hc194/simulation/presynth/_vmake
74hc194/simulation/run.do
74hc194/simulation/vsim.wlf
74hc194/smartgen/
74hc194/smartgen/smartgen.aws
74hc194/stimulus/
74hc194/stimulus/testbench.v
74hc194/synthesis/
74hc194/synthesis/.recordref
74hc194/synthesis/backup/
74hc194/synthesis/backup/shift4.srr
74hc194/synthesis/coreip/
74hc194/synthesis/run_options.txt
74hc194/synthesis/shift4.areasrr
74hc194/synthesis/shift4.edn
74hc194/synthesis/shift4.fse
74hc194/synthesis/shift4.htm
74hc194/synthesis/shift4.map
74hc194/synthesis/shift4.pdc
74hc194/synthesis/shift4.sap
74hc194/synthesis/shift4.sdf
74hc194/synthesis/shift4.so
74hc194/synthesis/shift4.srd
74hc194/synthesis/shift4.srm
74hc194/synthesis/shift4.srr
74hc194/synthesis/shift4.srs
74hc194/synthesis/shift4.szr
74hc194/synthesis/shift4.tlg
74hc194/synthesis/shift4_sdc.sdc
74hc194/synthesis/shift4_syn.prj
74hc194/synthesis/stdout.log
74hc194/synthesis/syntmp/
74hc194/synthesis/syntmp/sap.log
74hc194/synthesis/syntmp/shift4.plg
74hc194/synthesis/syntmp/shift4_flink.htm
74hc194/synthesis/syntmp/shift4_srr.htm
74hc194/synthesis/syntmp/shift4_toc.htm
74hc194/synthesis/traplog.tlg
74hc194/viewdraw/
74hc194/viewdraw/sch/
74hc194/viewdraw/sym/
74hc194/viewdraw/vf/
74hc194/viewdraw/vf/project.lst
74hc194/viewdraw/viewdraw.ini
74hc194/viewdraw/wir/
74hc194/
74hc194/74hc194.prj
74hc194/component/
74hc194/constraint/
74hc194/coreconsole/
74hc194/designer/
74hc194/designer/impl1/
74hc194/designer/impl1/designer.log
74hc194/designer/impl1/shift4.adb
74hc194/designer/impl1/shift4.dtf/
74hc194/designer/impl1/shift4.dtf/verify.log
74hc194/designer/impl1/shift4.ide_des
74hc194/designer/impl1/shift4.pdb
74hc194/designer/impl1/shift4.pdb.depends
74hc194/designer/impl1/shift4.tcl
74hc194/designer/impl1/shift4_fp/
74hc194/designer/impl1/shift4_fp/$$FlashPro_07294.L$$
74hc194/designer/impl1/shift4_fp/projectData/
74hc194/designer/impl1/shift4_fp/projectData/shift4.pdb
74hc194/designer/impl1/shift4_fp/shift4.log
74hc194/designer/impl1/shift4_fp/shift4.pro
74hc194/designer/impl1/simulation/
74hc194/hdl/
74hc194/hdl/74hc194.v
74hc194/phy_synthesis/
74hc194/simulation/
74hc194/simulation/modelsim.ini
74hc194/simulation/modelsim.ini.sav
74hc194/simulation/modelsim.log
74hc194/simulation/presynth/
74hc194/simulation/presynth/shift4/
74hc194/simulation/presynth/shift4/verilog.psm
74hc194/simulation/presynth/shift4/_primary.dat
74hc194/simulation/presynth/shift4/_primary.dbs
74hc194/simulation/presynth/shift4/_primary.vhd
74hc194/simulation/presynth/testbench/
74hc194/simulation/presynth/testbench/verilog.psm
74hc194/simulation/presynth/testbench/_primary.dat
74hc194/simulation/presynth/testbench/_primary.dbs
74hc194/simulation/presynth/testbench/_primary.vhd
74hc194/simulation/presynth/_info
74hc194/simulation/presynth/_temp/
74hc194/simulation/presynth/_vmake
74hc194/simulation/run.do
74hc194/simulation/vsim.wlf
74hc194/smartgen/
74hc194/smartgen/smartgen.aws
74hc194/stimulus/
74hc194/stimulus/testbench.v
74hc194/synthesis/
74hc194/synthesis/.recordref
74hc194/synthesis/backup/
74hc194/synthesis/backup/shift4.srr
74hc194/synthesis/coreip/
74hc194/synthesis/run_options.txt
74hc194/synthesis/shift4.areasrr
74hc194/synthesis/shift4.edn
74hc194/synthesis/shift4.fse
74hc194/synthesis/shift4.htm
74hc194/synthesis/shift4.map
74hc194/synthesis/shift4.pdc
74hc194/synthesis/shift4.sap
74hc194/synthesis/shift4.sdf
74hc194/synthesis/shift4.so
74hc194/synthesis/shift4.srd
74hc194/synthesis/shift4.srm
74hc194/synthesis/shift4.srr
74hc194/synthesis/shift4.srs
74hc194/synthesis/shift4.szr
74hc194/synthesis/shift4.tlg
74hc194/synthesis/shift4_sdc.sdc
74hc194/synthesis/shift4_syn.prj
74hc194/synthesis/stdout.log
74hc194/synthesis/syntmp/
74hc194/synthesis/syntmp/sap.log
74hc194/synthesis/syntmp/shift4.plg
74hc194/synthesis/syntmp/shift4_flink.htm
74hc194/synthesis/syntmp/shift4_srr.htm
74hc194/synthesis/syntmp/shift4_toc.htm
74hc194/synthesis/traplog.tlg
74hc194/viewdraw/
74hc194/viewdraw/sch/
74hc194/viewdraw/sym/
74hc194/viewdraw/vf/
74hc194/viewdraw/vf/project.lst
74hc194/viewdraw/viewdraw.ini
74hc194/viewdraw/wir/
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