文件名称:aemb.tar
-
所属分类:
- 标签属性:
- 上传时间:2012-11-16
-
文件大小:184.8kb
-
已下载:1次
-
提 供 者:
-
相关连接:无下载说明:别用迅雷下载,失败请重下,重下不扣分!
介绍说明--下载内容来自于网络,使用问题请自行百度
使用从互联网的信息aeMB是EDK3.2适合Microblaze核心的洁净室实施。 它是周期和指示适合对多数软件命令的MB。 因为它不是100 建筑上适合,没有意味,因为在替换的下落Microblaze的。 这是能够移动和操作数据到/从记忆的CPU核心。 它没有任何外围设备亦不中断控制器,虽然外在中断提供支持。 所有外围设备和他们的各自记数器能被映射到数据记忆或FSL存储量。 它有一辆分开的指示、数据和FSL公共汽车。 -The aeMB is a clean room implementation of the EDK3.2 compatible Microblaze core using information from the Internet. It is cycle and instruction compatible to the MB for most software commands. It is not meant as a drop in replacement for the Microblaze as it is not 100 architecturally compatible. This is a CPU core that is capable of moving and manipulating data to and from memory. It does not have any peripherals nor interrupt controllers although support for external interrupts is provided. Any peripherals and their respective registers could be mapped to the data memory or FSL memory space. It has a separate instruction, data and FSL buses.
(系统自动生成,下载前可以参看下载内容)
下载文件列表
aemb/
aemb/syn/
aemb/syn/CVS/
aemb/syn/CVS/Repository
aemb/syn/CVS/Entries
aemb/syn/CVS/Root
aemb/sw/
aemb/sw/aemb.specs
aemb/sw/cc/
aemb/sw/cc/aemb/
aemb/sw/cc/aemb/heap.hh
aemb/sw/cc/aemb/semaphore.hh
aemb/sw/cc/aemb/core.hh
aemb/sw/cc/aemb/hook.hh
aemb/sw/cc/aemb/msr.hh
aemb/sw/cc/aemb/CVS/
aemb/sw/cc/aemb/CVS/Repository
aemb/sw/cc/aemb/CVS/Entries
aemb/sw/cc/aemb/CVS/Root
aemb/sw/cc/aemb/thread.hh
aemb/sw/cc/aemb/stack.hh
aemb/sw/cc/aemb/stdio.hh
aemb/sw/cc/literate.hh
aemb/sw/cc/memtest.hh
aemb/sw/cc/testbench.cc
aemb/sw/cc/CVS/
aemb/sw/cc/CVS/Repository
aemb/sw/cc/CVS/Entries
aemb/sw/cc/CVS/Root
aemb/sw/cc/corefunc.hh
aemb/sw/cc/simboard.hh
aemb/sw/cc/bootstrap.c
aemb/sw/CVS/
aemb/sw/CVS/Repository
aemb/sw/CVS/Entries
aemb/sw/CVS/Root
aemb/sw/gccrom
aemb/sw/c/
aemb/sw/c/libaemb.h
aemb/sw/c/aeMB_testbench.c
aemb/sw/c/CVS/
aemb/sw/c/CVS/Repository
aemb/sw/c/CVS/Entries
aemb/sw/c/CVS/Root
aemb/sim/
aemb/sim/cversim
aemb/sim/php/
aemb/sim/php/simulator.php
aemb/sim/php/CVS/
aemb/sim/php/CVS/Repository
aemb/sim/php/CVS/Entries
aemb/sim/php/CVS/Root
aemb/sim/verilog/
aemb/sim/verilog/aemb2.v
aemb/sim/verilog/edk62.v
aemb/sim/verilog/edk32.v
aemb/sim/verilog/CVS/
aemb/sim/verilog/CVS/Repository
aemb/sim/verilog/CVS/Entries
aemb/sim/verilog/CVS/Root
aemb/sim/CVS/
aemb/sim/CVS/Repository
aemb/sim/CVS/Entries
aemb/sim/CVS/Root
aemb/sim/iversim
aemb/rtl/
aemb/rtl/verilog/
aemb/rtl/verilog/aeMB2_sysc.v
aemb/rtl/verilog/aeMB2_regf.v
aemb/rtl/verilog/aeMB2_regs.v
aemb/rtl/verilog/fasm_dpsram.v
aemb/rtl/verilog/aeMB_bpcu.v
aemb/rtl/verilog/aeMB2_bsft.v
aemb/rtl/verilog/aeMB2_brcc.v
aemb/rtl/verilog/fasm_tpsram.v
aemb/rtl/verilog/aeMB_core.v
aemb/rtl/verilog/fasm_sparam.v
aemb/rtl/verilog/aeMB2_mult.v
aemb/rtl/verilog/aeMB2_sparam.v
aemb/rtl/verilog/aeMB2_gprf.v
aemb/rtl/verilog/aeMB2_opmx.v
aemb/rtl/verilog/aeMB2_dwbif.v
aemb/rtl/verilog/aeMB2_tpsram.v
aemb/rtl/verilog/aeMB_sim.v
aemb/rtl/verilog/aeMB2_edk62.v
aemb/rtl/verilog/aeMB_regf.v
aemb/rtl/verilog/aeMB2_ctrl.v
aemb/rtl/verilog/aeMB2_spsram.v
aemb/rtl/verilog/aeMB2_iwbif.v
aemb/rtl/verilog/aeMB_xecu.v
aemb/rtl/verilog/aeMB2_ofid.v
aemb/rtl/verilog/fasm_spsram.v
aemb/rtl/verilog/aeMB_edk32.v
aemb/rtl/verilog/aeMB2_idmx.v
aemb/rtl/verilog/aeMB2_memif.v
aemb/rtl/verilog/aeMB2_intu.v
aemb/rtl/verilog/aeMB2_sfrf.v
aemb/rtl/verilog/aeMB2_pipe.v
aemb/rtl/verilog/aeMB2_aslu.v
aemb/rtl/verilog/aeMB2_exec.v
aemb/rtl/verilog/aeMB_ibuf.v
aemb/rtl/verilog/aeMB_dwbif.v
aemb/rtl/verilog/aeMB2_iche.v
aemb/rtl/verilog/CVS/
aemb/rtl/verilog/CVS/Repository
aemb/rtl/verilog/CVS/Entries
aemb/rtl/verilog/CVS/Root
aemb/rtl/verilog/aeMB2_bpcu.v
aemb/rtl/verilog/aeMB2_dparam.v
aemb/rtl/verilog/aeMB2_edk32.v
aemb/rtl/verilog/fasm_dparam.v
aemb/rtl/verilog/aeMB2_xslif.v
aemb/rtl/verilog/fasm_fifo.v
aemb/rtl/verilog/fasm_tparam.v
aemb/rtl/verilog/aeMB_ctrl.v
aemb/rtl/verilog/aeMB2_sim.v
aemb/rtl/CVS/
aemb/rtl/CVS/Repository
aemb/rtl/CVS/Entries
aemb/rtl/CVS/Root
aemb/doc/
aemb/doc/aeMB_datasheet.pdf
aemb/doc/CVS/
aemb/doc/CVS/Repository
aemb/doc/CVS/Entries
aemb/doc/CVS/Root
aemb/CVS/
aemb/CVS/Repository
aemb/CVS/Entries
aemb/CVS/Root
aemb/syn/
aemb/syn/CVS/
aemb/syn/CVS/Repository
aemb/syn/CVS/Entries
aemb/syn/CVS/Root
aemb/sw/
aemb/sw/aemb.specs
aemb/sw/cc/
aemb/sw/cc/aemb/
aemb/sw/cc/aemb/heap.hh
aemb/sw/cc/aemb/semaphore.hh
aemb/sw/cc/aemb/core.hh
aemb/sw/cc/aemb/hook.hh
aemb/sw/cc/aemb/msr.hh
aemb/sw/cc/aemb/CVS/
aemb/sw/cc/aemb/CVS/Repository
aemb/sw/cc/aemb/CVS/Entries
aemb/sw/cc/aemb/CVS/Root
aemb/sw/cc/aemb/thread.hh
aemb/sw/cc/aemb/stack.hh
aemb/sw/cc/aemb/stdio.hh
aemb/sw/cc/literate.hh
aemb/sw/cc/memtest.hh
aemb/sw/cc/testbench.cc
aemb/sw/cc/CVS/
aemb/sw/cc/CVS/Repository
aemb/sw/cc/CVS/Entries
aemb/sw/cc/CVS/Root
aemb/sw/cc/corefunc.hh
aemb/sw/cc/simboard.hh
aemb/sw/cc/bootstrap.c
aemb/sw/CVS/
aemb/sw/CVS/Repository
aemb/sw/CVS/Entries
aemb/sw/CVS/Root
aemb/sw/gccrom
aemb/sw/c/
aemb/sw/c/libaemb.h
aemb/sw/c/aeMB_testbench.c
aemb/sw/c/CVS/
aemb/sw/c/CVS/Repository
aemb/sw/c/CVS/Entries
aemb/sw/c/CVS/Root
aemb/sim/
aemb/sim/cversim
aemb/sim/php/
aemb/sim/php/simulator.php
aemb/sim/php/CVS/
aemb/sim/php/CVS/Repository
aemb/sim/php/CVS/Entries
aemb/sim/php/CVS/Root
aemb/sim/verilog/
aemb/sim/verilog/aemb2.v
aemb/sim/verilog/edk62.v
aemb/sim/verilog/edk32.v
aemb/sim/verilog/CVS/
aemb/sim/verilog/CVS/Repository
aemb/sim/verilog/CVS/Entries
aemb/sim/verilog/CVS/Root
aemb/sim/CVS/
aemb/sim/CVS/Repository
aemb/sim/CVS/Entries
aemb/sim/CVS/Root
aemb/sim/iversim
aemb/rtl/
aemb/rtl/verilog/
aemb/rtl/verilog/aeMB2_sysc.v
aemb/rtl/verilog/aeMB2_regf.v
aemb/rtl/verilog/aeMB2_regs.v
aemb/rtl/verilog/fasm_dpsram.v
aemb/rtl/verilog/aeMB_bpcu.v
aemb/rtl/verilog/aeMB2_bsft.v
aemb/rtl/verilog/aeMB2_brcc.v
aemb/rtl/verilog/fasm_tpsram.v
aemb/rtl/verilog/aeMB_core.v
aemb/rtl/verilog/fasm_sparam.v
aemb/rtl/verilog/aeMB2_mult.v
aemb/rtl/verilog/aeMB2_sparam.v
aemb/rtl/verilog/aeMB2_gprf.v
aemb/rtl/verilog/aeMB2_opmx.v
aemb/rtl/verilog/aeMB2_dwbif.v
aemb/rtl/verilog/aeMB2_tpsram.v
aemb/rtl/verilog/aeMB_sim.v
aemb/rtl/verilog/aeMB2_edk62.v
aemb/rtl/verilog/aeMB_regf.v
aemb/rtl/verilog/aeMB2_ctrl.v
aemb/rtl/verilog/aeMB2_spsram.v
aemb/rtl/verilog/aeMB2_iwbif.v
aemb/rtl/verilog/aeMB_xecu.v
aemb/rtl/verilog/aeMB2_ofid.v
aemb/rtl/verilog/fasm_spsram.v
aemb/rtl/verilog/aeMB_edk32.v
aemb/rtl/verilog/aeMB2_idmx.v
aemb/rtl/verilog/aeMB2_memif.v
aemb/rtl/verilog/aeMB2_intu.v
aemb/rtl/verilog/aeMB2_sfrf.v
aemb/rtl/verilog/aeMB2_pipe.v
aemb/rtl/verilog/aeMB2_aslu.v
aemb/rtl/verilog/aeMB2_exec.v
aemb/rtl/verilog/aeMB_ibuf.v
aemb/rtl/verilog/aeMB_dwbif.v
aemb/rtl/verilog/aeMB2_iche.v
aemb/rtl/verilog/CVS/
aemb/rtl/verilog/CVS/Repository
aemb/rtl/verilog/CVS/Entries
aemb/rtl/verilog/CVS/Root
aemb/rtl/verilog/aeMB2_bpcu.v
aemb/rtl/verilog/aeMB2_dparam.v
aemb/rtl/verilog/aeMB2_edk32.v
aemb/rtl/verilog/fasm_dparam.v
aemb/rtl/verilog/aeMB2_xslif.v
aemb/rtl/verilog/fasm_fifo.v
aemb/rtl/verilog/fasm_tparam.v
aemb/rtl/verilog/aeMB_ctrl.v
aemb/rtl/verilog/aeMB2_sim.v
aemb/rtl/CVS/
aemb/rtl/CVS/Repository
aemb/rtl/CVS/Entries
aemb/rtl/CVS/Root
aemb/doc/
aemb/doc/aeMB_datasheet.pdf
aemb/doc/CVS/
aemb/doc/CVS/Repository
aemb/doc/CVS/Entries
aemb/doc/CVS/Root
aemb/CVS/
aemb/CVS/Repository
aemb/CVS/Entries
aemb/CVS/Root
本网站为编程资源及源代码搜集、介绍的搜索网站,版权归原作者所有! 粤ICP备11031372号
1999-2046 搜珍网 All Rights Reserved.