这是一个用VHDL编写的占空比可调的程序，对一个刚刚入门的FPGA的学员来说可以起到一个引导作用，简单但能学到很多东西-This is a VHDL prepared with adjustable duty cycle of the process, just getting started on a FPGA for the students can play a guiding role, a simple but can learn a lot