文件名称:FreCore8051
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- 上传时间:2012-11-16
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文件大小:10.66mb
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已下载:0次
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相关连接:无下载说明:别用迅雷下载,失败请重下,重下不扣分!
介绍说明--下载内容来自于网络,使用问题请自行百度
基于ACTEL FPGA的测频模块,测频精度非常高!-ACTEL FPGA-based module of the frequency measurement, frequency measurement accuracy is very high!
(系统自动生成,下载前可以参看下载内容)
下载文件列表
FreCore8051/core8051.prj
FreCore8051/core8051.prj.convert.8.0.bak
FreCore8051/core8051.prj.convert.8.1.bak
FreCore8051/12345678.hex
FreCore8051/sss.hex
FreCore8051/test.hex
FreCore8051/lsd.hex
FreCore8051/stimulus/testbench.v
FreCore8051/stimulus/USER_CORE8051.hpj
FreCore8051/stimulus/waveperl.log
FreCore8051/stimulus/BtimErrors.log
FreCore8051/stimulus/files_to_build.txt
FreCore8051/stimulus/USER_CORE8051.dsk
FreCore8051/stimulus/ModelUnderTest_tbench.btim
FreCore8051/stimulus/ModelUnderTest_tbench.bk
FreCore8051/constraint/USER_CORE8051.pdc
FreCore8051/constraint/USER_CORE8051_sdc.sdc
FreCore8051/designer/impl1/designer.log
FreCore8051/designer/impl1/designer_genhdl.log
FreCore8051/designer/impl1/USER_CORE8051.ide_des
FreCore8051/designer/impl1/USER_CORE8051.pdb
FreCore8051/designer/impl1/USER_CORE8051.pdb.depends
FreCore8051/designer/impl1/USER_CORE8051.tcl
FreCore8051/designer/impl1/USER_CORE8051_ba.sdf
FreCore8051/designer/impl1/USER_CORE8051_ba.v
FreCore8051/designer/impl1/designer_gen_ba.log
FreCore8051/designer/impl1/USER_CORE8051_fp/USER_CORE8051.log
FreCore8051/designer/impl1/USER_CORE8051_fp/$$FlashPro_FPBBALTLPT1.L$$
FreCore8051/designer/impl1/USER_CORE8051_fp/af264.ini
FreCore8051/designer/impl1/USER_CORE8051_fp/af268.efc1
FreCore8051/designer/impl1/USER_CORE8051_fp/projectData/USER_CORE8051.pdb.depends
FreCore8051/designer/impl1/USER_CORE8051_fp/projectData/USER_CORE8051.pdb
FreCore8051/designer/impl1/USER_CORE8051_fp/USER_CORE8051.pro
FreCore8051/designer/impl1/USER_CORE8051_fp/$$FlashPro_08284.L$$
FreCore8051/designer/impl1/USER_CORE8051_fp/af275.efc1
FreCore8051/designer/impl1/USER_CORE8051_fp/af271.ini
FreCore8051/designer/impl1/USER_CORE8051.dtf/verify.log
FreCore8051/designer/impl1/simulation/postlayout/_info
FreCore8051/designer/impl1/simulation/postlayout/testbench/_primary.vhd
FreCore8051/designer/impl1/simulation/postlayout/testbench/verilog.psm
FreCore8051/designer/impl1/simulation/postlayout/testbench/_primary.dbs
FreCore8051/designer/impl1/simulation/postlayout/testbench/_primary.dat
FreCore8051/designer/impl1/simulation/postlayout/@u@s@e@r_@c@o@r@e8051/_primary.vhd
FreCore8051/designer/impl1/simulation/postlayout/@u@s@e@r_@c@o@r@e8051/verilog.psm
FreCore8051/designer/impl1/simulation/postlayout/@u@s@e@r_@c@o@r@e8051/_primary.dbs
FreCore8051/designer/impl1/simulation/postlayout/@u@s@e@r_@c@o@r@e8051/_primary.dat
FreCore8051/designer/impl1/USER_CORE8051.adb
FreCore8051/designer/impl1/USER_CORE8051_1.ide_des
FreCore8051/designer/impl1/USER_CORE8051_1.adb
FreCore8051/designer/impl1/sdcrd.log
FreCore8051/designer/impl1/USER_CORE8051_2.ide_des
FreCore8051/designer/impl1/USER_CORE8051_2.adb
FreCore8051/hdl/core8051_oci0_withoutio_pa3.v
FreCore8051/hdl/Core8051_ROM_Ctr.v
FreCore8051/hdl/analog_top.v
FreCore8051/hdl/key.v
FreCore8051/hdl/BUZZER_LED.v
FreCore8051/hdl/user_core8051.v
FreCore8051/hdl/filter.v
FreCore8051/hdl/frequence.v
FreCore8051/simulation/flashmem_test.hex
FreCore8051/simulation/meminit.dat
FreCore8051/simulation/flashmem_12345678.hex
FreCore8051/simulation/flashmem_sss.hex
FreCore8051/simulation/flashmem_lsd.hex
FreCore8051/simulation/run.do
FreCore8051/simulation/modelsim.log
FreCore8051/simulation/vsim.wlf
FreCore8051/simulation/flashmem_1602.hex
FreCore8051/simulation/analog_acm_ram_R0C0.mem
FreCore8051/simulation/analog_assc_ram_R0C0.mem
FreCore8051/simulation/analog_smev_ram_R0C0.mem
FreCore8051/simulation/analog_smtr_ram_R0C0.mem
FreCore8051/simulation/flashmem_analog.mem
FreCore8051/simulation/flashmem.mem
FreCore8051/simulation/RAM2K_R0C0.mem
FreCore8051/simulation/RAM2K_R0C1.mem
FreCore8051/simulation/RAM2K_R0C2.mem
FreCore8051/simulation/RAM2K_R0C3.mem
FreCore8051/simulation/RAM256X8_R0C0.mem
FreCore8051/simulation/test.cr.mti
FreCore8051/simulation/modelsim.ini
FreCore8051/simulation/fre.v
FreCore8051/simulation/postsynth/_info
FreCore8051/simulation/postsynth/key/_primary.vhd
FreCore8051/simulation/postsynth/key/verilog.psm
FreCore8051/simulation/postsynth/key/_primary.dbs
FreCore8051/simulation/postsynth/key/_primary.dat
FreCore8051/simulation/postsynth/testbench/_primary.vhd
FreCore8051/simulation/postsynth/testbench/verilog.psm
FreCore8051/simulation/postsynth/testbench/_primary.dbs
FreCore8051/simulation/postsynth/testbench/_primary.dat
FreCore8051/simulation/postsynth/@u@s@e@r_@c@o@r@e8051/_primary.vhd
FreCore8051/simulation/postsynth/@u@s@e@r_@c@o@r@e8051/verilog.psm
FreCore8051/simulation/postsynth/@u@s@e@r_@c@o@r@e8051/_primary.dbs
FreCore8051/simulation/postsynth/@u@s@e@r_@c@o@r@e8051/_primary.dat
FreCore8051/simulation/postsynth/@core8051_@r@o@m_@ctr/_primary.vhd
FreCore8051/simulation/postsynth/@core8051_@r@o@m_@ctr/verilog.psm
FreCore8051/simulation/postsynth/@core8051_@r@o@m_@ctr/_primary.dbs
FreCore8051/simulation/postsynth/@core8051_@r@o@m_@ctr/_primary.dat
FreCore8051/simulation/postsynth/@r@a@m256@x8/_primary.vhd
FreCore8051/simulation/postsynth/@r@a@m256@x8/verilog.psm
FreCore8051/simulation/postsynth/@r@a@m256@x8/_primary.dbs
FreCore8051/simulation/postsynth/@r@a@m256@x8/_primary.dat
FreCore8051/simulation/postsynth/flashmem/_primary.vhd
FreCore8051/simulat
FreCore8051/core8051.prj.convert.8.0.bak
FreCore8051/core8051.prj.convert.8.1.bak
FreCore8051/12345678.hex
FreCore8051/sss.hex
FreCore8051/test.hex
FreCore8051/lsd.hex
FreCore8051/stimulus/testbench.v
FreCore8051/stimulus/USER_CORE8051.hpj
FreCore8051/stimulus/waveperl.log
FreCore8051/stimulus/BtimErrors.log
FreCore8051/stimulus/files_to_build.txt
FreCore8051/stimulus/USER_CORE8051.dsk
FreCore8051/stimulus/ModelUnderTest_tbench.btim
FreCore8051/stimulus/ModelUnderTest_tbench.bk
FreCore8051/constraint/USER_CORE8051.pdc
FreCore8051/constraint/USER_CORE8051_sdc.sdc
FreCore8051/designer/impl1/designer.log
FreCore8051/designer/impl1/designer_genhdl.log
FreCore8051/designer/impl1/USER_CORE8051.ide_des
FreCore8051/designer/impl1/USER_CORE8051.pdb
FreCore8051/designer/impl1/USER_CORE8051.pdb.depends
FreCore8051/designer/impl1/USER_CORE8051.tcl
FreCore8051/designer/impl1/USER_CORE8051_ba.sdf
FreCore8051/designer/impl1/USER_CORE8051_ba.v
FreCore8051/designer/impl1/designer_gen_ba.log
FreCore8051/designer/impl1/USER_CORE8051_fp/USER_CORE8051.log
FreCore8051/designer/impl1/USER_CORE8051_fp/$$FlashPro_FPBBALTLPT1.L$$
FreCore8051/designer/impl1/USER_CORE8051_fp/af264.ini
FreCore8051/designer/impl1/USER_CORE8051_fp/af268.efc1
FreCore8051/designer/impl1/USER_CORE8051_fp/projectData/USER_CORE8051.pdb.depends
FreCore8051/designer/impl1/USER_CORE8051_fp/projectData/USER_CORE8051.pdb
FreCore8051/designer/impl1/USER_CORE8051_fp/USER_CORE8051.pro
FreCore8051/designer/impl1/USER_CORE8051_fp/$$FlashPro_08284.L$$
FreCore8051/designer/impl1/USER_CORE8051_fp/af275.efc1
FreCore8051/designer/impl1/USER_CORE8051_fp/af271.ini
FreCore8051/designer/impl1/USER_CORE8051.dtf/verify.log
FreCore8051/designer/impl1/simulation/postlayout/_info
FreCore8051/designer/impl1/simulation/postlayout/testbench/_primary.vhd
FreCore8051/designer/impl1/simulation/postlayout/testbench/verilog.psm
FreCore8051/designer/impl1/simulation/postlayout/testbench/_primary.dbs
FreCore8051/designer/impl1/simulation/postlayout/testbench/_primary.dat
FreCore8051/designer/impl1/simulation/postlayout/@u@s@e@r_@c@o@r@e8051/_primary.vhd
FreCore8051/designer/impl1/simulation/postlayout/@u@s@e@r_@c@o@r@e8051/verilog.psm
FreCore8051/designer/impl1/simulation/postlayout/@u@s@e@r_@c@o@r@e8051/_primary.dbs
FreCore8051/designer/impl1/simulation/postlayout/@u@s@e@r_@c@o@r@e8051/_primary.dat
FreCore8051/designer/impl1/USER_CORE8051.adb
FreCore8051/designer/impl1/USER_CORE8051_1.ide_des
FreCore8051/designer/impl1/USER_CORE8051_1.adb
FreCore8051/designer/impl1/sdcrd.log
FreCore8051/designer/impl1/USER_CORE8051_2.ide_des
FreCore8051/designer/impl1/USER_CORE8051_2.adb
FreCore8051/hdl/core8051_oci0_withoutio_pa3.v
FreCore8051/hdl/Core8051_ROM_Ctr.v
FreCore8051/hdl/analog_top.v
FreCore8051/hdl/key.v
FreCore8051/hdl/BUZZER_LED.v
FreCore8051/hdl/user_core8051.v
FreCore8051/hdl/filter.v
FreCore8051/hdl/frequence.v
FreCore8051/simulation/flashmem_test.hex
FreCore8051/simulation/meminit.dat
FreCore8051/simulation/flashmem_12345678.hex
FreCore8051/simulation/flashmem_sss.hex
FreCore8051/simulation/flashmem_lsd.hex
FreCore8051/simulation/run.do
FreCore8051/simulation/modelsim.log
FreCore8051/simulation/vsim.wlf
FreCore8051/simulation/flashmem_1602.hex
FreCore8051/simulation/analog_acm_ram_R0C0.mem
FreCore8051/simulation/analog_assc_ram_R0C0.mem
FreCore8051/simulation/analog_smev_ram_R0C0.mem
FreCore8051/simulation/analog_smtr_ram_R0C0.mem
FreCore8051/simulation/flashmem_analog.mem
FreCore8051/simulation/flashmem.mem
FreCore8051/simulation/RAM2K_R0C0.mem
FreCore8051/simulation/RAM2K_R0C1.mem
FreCore8051/simulation/RAM2K_R0C2.mem
FreCore8051/simulation/RAM2K_R0C3.mem
FreCore8051/simulation/RAM256X8_R0C0.mem
FreCore8051/simulation/test.cr.mti
FreCore8051/simulation/modelsim.ini
FreCore8051/simulation/fre.v
FreCore8051/simulation/postsynth/_info
FreCore8051/simulation/postsynth/key/_primary.vhd
FreCore8051/simulation/postsynth/key/verilog.psm
FreCore8051/simulation/postsynth/key/_primary.dbs
FreCore8051/simulation/postsynth/key/_primary.dat
FreCore8051/simulation/postsynth/testbench/_primary.vhd
FreCore8051/simulation/postsynth/testbench/verilog.psm
FreCore8051/simulation/postsynth/testbench/_primary.dbs
FreCore8051/simulation/postsynth/testbench/_primary.dat
FreCore8051/simulation/postsynth/@u@s@e@r_@c@o@r@e8051/_primary.vhd
FreCore8051/simulation/postsynth/@u@s@e@r_@c@o@r@e8051/verilog.psm
FreCore8051/simulation/postsynth/@u@s@e@r_@c@o@r@e8051/_primary.dbs
FreCore8051/simulation/postsynth/@u@s@e@r_@c@o@r@e8051/_primary.dat
FreCore8051/simulation/postsynth/@core8051_@r@o@m_@ctr/_primary.vhd
FreCore8051/simulation/postsynth/@core8051_@r@o@m_@ctr/verilog.psm
FreCore8051/simulation/postsynth/@core8051_@r@o@m_@ctr/_primary.dbs
FreCore8051/simulation/postsynth/@core8051_@r@o@m_@ctr/_primary.dat
FreCore8051/simulation/postsynth/@r@a@m256@x8/_primary.vhd
FreCore8051/simulation/postsynth/@r@a@m256@x8/verilog.psm
FreCore8051/simulation/postsynth/@r@a@m256@x8/_primary.dbs
FreCore8051/simulation/postsynth/@r@a@m256@x8/_primary.dat
FreCore8051/simulation/postsynth/flashmem/_primary.vhd
FreCore8051/simulat
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