文件名称:usb_phy_verilog.tar
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- 上传时间：2012-11-16
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文件大小：7.21kb
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usb的逻辑设计代码，供大家研究或使用，参考-the logic design usb code, or use for your research, reference
相关搜索： VHDL USB
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下载文件列表
usb_phy/
usb_phy/rtl/
usb_phy/rtl/verilog/
usb_phy/rtl/verilog/usb_tx_phy.v
usb_phy/rtl/verilog/CVS/
usb_phy/rtl/verilog/CVS/Repository
usb_phy/rtl/verilog/CVS/Entries
usb_phy/rtl/verilog/CVS/Root
usb_phy/rtl/verilog/usb_rx_phy.v
usb_phy/rtl/verilog/usb_phy.v
usb_phy/rtl/verilog/timescale.v
usb_phy/rtl/CVS/
usb_phy/rtl/CVS/Repository
usb_phy/rtl/CVS/Entries
usb_phy/rtl/CVS/Root
usb_phy/doc/
usb_phy/doc/README.txt
usb_phy/doc/CVS/
usb_phy/doc/CVS/Repository
usb_phy/doc/CVS/Entries
usb_phy/doc/CVS/Root
usb_phy/CVS/
usb_phy/CVS/Repository
usb_phy/CVS/Entries
usb_phy/CVS/Root
usb_phy/rtl/
usb_phy/rtl/verilog/
usb_phy/rtl/verilog/usb_tx_phy.v
usb_phy/rtl/verilog/CVS/
usb_phy/rtl/verilog/CVS/Repository
usb_phy/rtl/verilog/CVS/Entries
usb_phy/rtl/verilog/CVS/Root
usb_phy/rtl/verilog/usb_rx_phy.v
usb_phy/rtl/verilog/usb_phy.v
usb_phy/rtl/verilog/timescale.v
usb_phy/rtl/CVS/
usb_phy/rtl/CVS/Repository
usb_phy/rtl/CVS/Entries
usb_phy/rtl/CVS/Root
usb_phy/doc/
usb_phy/doc/README.txt
usb_phy/doc/CVS/
usb_phy/doc/CVS/Repository
usb_phy/doc/CVS/Entries
usb_phy/doc/CVS/Root
usb_phy/CVS/
usb_phy/CVS/Repository
usb_phy/CVS/Entries
usb_phy/CVS/Root
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