文件名称:alu
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- 上传时间:2012-11-16
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文件大小:533.38kb
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ALU modeling verilog codes and testbench
相关搜索: alu verilog
alu testbench
verilog ALU
ALU
testbench verilog
test bench vhdl code a
verilog testbench
TestBench
verilog codes
alu verilog with testbench
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下载文件列表
ADS/
ADS/ahb_slave_include.v
ADS/arm_top.bdf
ADS/pld_slave.bdf
ADS/pld_slave.BSF
ADS/simulation/
ADS/simulation/modelsim/
ADS/simulation/modelsim/bfm_wave.do
ADS/simulation/modelsim/edit_mpf.txt
ADS/simulation/modelsim/fullmodel_wave.do
ADS/simulation/modelsim/input.dat
ADS/simulation/modelsim/run_rtl_bfm_sim.do
ADS/simulation/modelsim/run_timing_bfm_sim.do
ADS/simulation/modelsim/slavememory.cfg.dat
ADS/software/
ADS/software/tutorial_code.s
GNU/
GNU/ahb_slave_include.v
GNU/arm_top.bdf
GNU/pld_slave.bdf
GNU/pld_slave.BSF
GNU/simulation/
GNU/simulation/modelsim/
GNU/simulation/modelsim/bfm_wave.do
GNU/simulation/modelsim/edit_mpf.txt
GNU/simulation/modelsim/fullmodel_wave.do
GNU/simulation/modelsim/input.dat
GNU/simulation/modelsim/run_rtl_bfm_sim.do
GNU/simulation/modelsim/run_timing_bfm_sim.do
GNU/simulation/modelsim/slavememory.cfg.dat
GNU/software/
GNU/software/tutorial_code.s
rtl/
rtl/ahb_slave_include.v
rtl/ahb_slave_sm.v
rtl/alu.v
rtl/pld_slave.v
rtl/regfile.v
testbench/
testbench/arm_top_tb.v
ug_arm_hardware_design-v1.5.pdf
ADS/software/uartcomm.c
ADS/software/uartcomm.h
ADS/software/alu_demo.c
ADS/software/armc_startup.S
ADS/software/int_ctrl00.h
ADS/software/irq.c
ADS/software/retarget.c
ADS/software/uart00.h
ADS/ahb_slave_include.v
ADS/arm_top.bdf
ADS/pld_slave.bdf
ADS/pld_slave.BSF
ADS/simulation/
ADS/simulation/modelsim/
ADS/simulation/modelsim/bfm_wave.do
ADS/simulation/modelsim/edit_mpf.txt
ADS/simulation/modelsim/fullmodel_wave.do
ADS/simulation/modelsim/input.dat
ADS/simulation/modelsim/run_rtl_bfm_sim.do
ADS/simulation/modelsim/run_timing_bfm_sim.do
ADS/simulation/modelsim/slavememory.cfg.dat
ADS/software/
ADS/software/tutorial_code.s
GNU/
GNU/ahb_slave_include.v
GNU/arm_top.bdf
GNU/pld_slave.bdf
GNU/pld_slave.BSF
GNU/simulation/
GNU/simulation/modelsim/
GNU/simulation/modelsim/bfm_wave.do
GNU/simulation/modelsim/edit_mpf.txt
GNU/simulation/modelsim/fullmodel_wave.do
GNU/simulation/modelsim/input.dat
GNU/simulation/modelsim/run_rtl_bfm_sim.do
GNU/simulation/modelsim/run_timing_bfm_sim.do
GNU/simulation/modelsim/slavememory.cfg.dat
GNU/software/
GNU/software/tutorial_code.s
rtl/
rtl/ahb_slave_include.v
rtl/ahb_slave_sm.v
rtl/alu.v
rtl/pld_slave.v
rtl/regfile.v
testbench/
testbench/arm_top_tb.v
ug_arm_hardware_design-v1.5.pdf
ADS/software/uartcomm.c
ADS/software/uartcomm.h
ADS/software/alu_demo.c
ADS/software/armc_startup.S
ADS/software/int_ctrl00.h
ADS/software/irq.c
ADS/software/retarget.c
ADS/software/uart00.h
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