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文件名称:sdram_control

  • 所属分类：
    Other systems
  • 标签属性：
    [ASM] [源码]
  • 上传时间：
    2012-11-16
  • 文件大小：
    3.47mb
  • 已下载：
    0次
  • 提 供 者：
    冯****
  • 相关连接：
    无
  • 下载说明：
    别用迅雷下载，失败请重下，重下不扣分！
修正介绍说明

介绍说明－－下载内容来自于网络，使用问题请自行百度

sdram 控制器的源代码及说明文档，综合，仿真。是一个很好的sdram控制器学习资料-provide sdram controller source code and documentation, integration, simulation. Is a very good learning materials about sdram controller
相关搜索： sdram 控制器 sdram控制器 SDRAM datacnl

(系统自动生成,下载前可以参看下载内容)

下载文件列表

sdram_control/src/Command.v
sdram_control/src/control_interface.v
sdram_control/src/datacnl.v.bak
sdram_control/src/Params.v
sdram_control/src/sdram_test_tb.v.bak
sdram_control/src/sdr_data_path.v
sdram_control/src/sdr_sdram.v
sdram_control/sim/altera_mf.v
sdram_control/sim/mt48lc2m32b2.v
sdram_control/sim/Params.v
sdram_control/sim/sdram_test.wlf
sdram_control/sim/sdram_test_tb.v
sdram_control/sim/sdram_test_tb.v.bak
sdram_control/sim/work/_info
sdram_control/sim/work/stx_scale_cntr/verilog.asm
sdram_control/sim/work/stx_scale_cntr/_primary.dat
sdram_control/sim/work/stx_scale_cntr/_primary.vhd
sdram_control/sim/work/stx_n_cntr/verilog.asm
sdram_control/sim/work/stx_n_cntr/_primary.dat
sdram_control/sim/work/stx_n_cntr/_primary.vhd
sdram_control/sim/work/stx_m_cntr/verilog.asm
sdram_control/sim/work/stx_m_cntr/_primary.dat
sdram_control/sim/work/stx_m_cntr/_primary.vhd
sdram_control/sim/work/stratix_lvds_rx/verilog.asm
sdram_control/sim/work/stratix_lvds_rx/_primary.dat
sdram_control/sim/work/stratix_lvds_rx/_primary.vhd
sdram_control/sim/work/stratixii_tx_outclk/verilog.asm
sdram_control/sim/work/stratixii_tx_outclk/_primary.dat
sdram_control/sim/work/stratixii_tx_outclk/_primary.vhd
sdram_control/sim/work/stratixii_lvds_rx/verilog.asm
sdram_control/sim/work/stratixii_lvds_rx/_primary.dat
sdram_control/sim/work/stratixii_lvds_rx/_primary.vhd
sdram_control/sim/work/stratixgx_dpa_lvds_rx/verilog.asm
sdram_control/sim/work/stratixgx_dpa_lvds_rx/_primary.dat
sdram_control/sim/work/stratixgx_dpa_lvds_rx/_primary.vhd
sdram_control/sim/work/sdr_sdram/verilog.asm
sdram_control/sim/work/sdr_sdram/_primary.dat
sdram_control/sim/work/sdr_sdram/_primary.vhd
sdram_control/sim/work/sdr_data_path/verilog.asm
sdram_control/sim/work/sdr_data_path/_primary.dat
sdram_control/sim/work/sdr_data_path/_primary.vhd
sdram_control/sim/work/sdram_test_tb/verilog.asm
sdram_control/sim/work/sdram_test_tb/_primary.dat
sdram_control/sim/work/sdram_test_tb/_primary.vhd
sdram_control/sim/work/scfifo/verilog.asm
sdram_control/sim/work/scfifo/_primary.dat
sdram_control/sim/work/scfifo/_primary.vhd
sdram_control/sim/work/parallel_add/verilog.asm
sdram_control/sim/work/parallel_add/_primary.dat
sdram_control/sim/work/parallel_add/_primary.vhd
sdram_control/sim/work/mt48lc2m32b2/verilog.asm
sdram_control/sim/work/mt48lc2m32b2/_primary.dat
sdram_control/sim/work/mt48lc2m32b2/_primary.vhd
sdram_control/sim/work/lcell/verilog.asm
sdram_control/sim/work/lcell/_primary.dat
sdram_control/sim/work/lcell/_primary.vhd
sdram_control/sim/work/hssi_tx/verilog.asm
sdram_control/sim/work/hssi_tx/_primary.dat
sdram_control/sim/work/hssi_tx/_primary.vhd
sdram_control/sim/work/hssi_rx/verilog.asm
sdram_control/sim/work/hssi_rx/_primary.dat
sdram_control/sim/work/hssi_rx/_primary.vhd
sdram_control/sim/work/hssi_pll/verilog.asm
sdram_control/sim/work/hssi_pll/_primary.dat
sdram_control/sim/work/hssi_pll/_primary.vhd
sdram_control/sim/work/hssi_fifo/verilog.asm
sdram_control/sim/work/hssi_fifo/_primary.dat
sdram_control/sim/work/hssi_fifo/_primary.vhd
sdram_control/sim/work/global/verilog.asm
sdram_control/sim/work/global/_primary.dat
sdram_control/sim/work/global/_primary.vhd
sdram_control/sim/work/exp/verilog.asm
sdram_control/sim/work/exp/_primary.dat
sdram_control/sim/work/exp/_primary.vhd
sdram_control/sim/work/dffp/verilog.asm
sdram_control/sim/work/dffp/_primary.dat
sdram_control/sim/work/dffp/_primary.vhd
sdram_control/sim/work/dcfifo_sync/verilog.asm
sdram_control/sim/work/dcfifo_sync/_primary.dat
sdram_control/sim/work/dcfifo_sync/_primary.vhd
sdram_control/sim/work/dcfifo_fefifo/verilog.asm
sdram_control/sim/work/dcfifo_fefifo/_primary.dat
sdram_control/sim/work/dcfifo_fefifo/_primary.vhd
sdram_control/sim/work/dcfifo_dffpipe/verilog.asm
sdram_control/sim/work/dcfifo_dffpipe/_primary.dat
sdram_control/sim/work/dcfifo_dffpipe/_primary.vhd
sdram_control/sim/work/dcfifo_async/verilog.asm
sdram_control/sim/work/dcfifo_async/_primary.dat
sdram_control/sim/work/dcfifo_async/_primary.vhd
sdram_control/sim/work/dcfifo/verilog.asm
sdram_control/sim/work/dcfifo/_primary.dat
sdram_control/sim/work/dcfifo/_primary.vhd
sdram_control/sim/work/control_interface/verilog.asm
sdram_control/sim/work/control_interface/_primary.dat
sdram_control/sim/work/control_interface/_primary.vhd
sdram_control/sim/work/command/verilog.asm
sdram_control/sim/work/command/_primary.dat
sdram_control/sim/work/command/_primary.vhd
sdram_control/sim/work/cascade/verilog.asm
sdram_control/sim/work/cascade/_primary.dat
sdram_control/sim/work/cascade/_primary.vhd
sdram_control/sim/work/carry_sum/verilog.asm
sdram_control/sim/work/carry_sum/_primary.dat
sdram_control/sim/work/carry_sum/_primary.vhd
sdram_control/sim/work/carry/verilog.asm
sdram_control/sim/work/carry/_primary.dat
sdram_control/sim/work/carry/_primary.vhd
sdram_control/sim/work/a_graycounter/verilog.asm
sdram_control/sim/work/a_graycounter/_primary.dat
sdram_control/sim/work/a_graycounter/_primary.vhd
sdram_control/sim/work/arm_scale_cntr/verilog.asm
sdram_control/sim/work/arm_scale_cntr/_primary.dat
sdram_control/sim/work/arm_scale_cntr/_primary

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