FPGA/keyboard interface is shown in figure 1. When the FPGA “reads” the Data or

Clock inputs both PS2Data_out and PS2Clk_out are kept low which puts the tri-state buffers

in high impedance mode. When the FPGA "writes" a logic 0 on an output, the corresponding

x_out (x = PS2Data or PS2Clk) signal is set high which pulls the line low. When “writing”

logic 1 the FPGA simply sets the x_out signal low.