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文件名称:auk_sdsdi

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  • 上传时间:
    2012-11-16
  • 文件大小:
    224.12kb
  • 已下载:
    6次
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介绍说明--下载内容来自于网络,使用问题请自行百度

用于FPGA设计的代码(Verilog代码),在FPGA设计中的高速串并转换,时钟提取,对齐处理等功能-for FPGA design ,written by Verilog HDL the functions include SERDES , CDR and so on
(系统自动生成,下载前可以参看下载内容)

下载文件列表

auk_sdsdi-v1.1
auk_sdsdi-v1.1/doc
auk_sdsdi-v1.1/doc/an356.pdf
auk_sdsdi-v1.1/doc/readme.txt
auk_sdsdi-v1.1/quartus
auk_sdsdi-v1.1/quartus/sdsdi_rxtx_cyclone_board
auk_sdsdi-v1.1/quartus/sdsdi_rxtx_cyclone_board/sdsdi_rxtx_cyclone_board.qpf
auk_sdsdi-v1.1/quartus/sdsdi_rxtx_cyclone_board/sdsdi_rxtx_cyclone_board.qsf
auk_sdsdi-v1.1/quartus/sdsdi_rxtx_demoboard
auk_sdsdi-v1.1/quartus/sdsdi_rxtx_demoboard/sclk_pll_x50_4.v
auk_sdsdi-v1.1/quartus/sdsdi_rxtx_demoboard/sdsdi_rxtx_demoboard.qpf
auk_sdsdi-v1.1/quartus/sdsdi_rxtx_demoboard/sdsdi_rxtx_demoboard.qsf
auk_sdsdi-v1.1/simulate
auk_sdsdi-v1.1/simulate/tb_sdsdi_rxtx
auk_sdsdi-v1.1/simulate/tb_sdsdi_rxtx/run.bat
auk_sdsdi-v1.1/simulate/tb_sdsdi_rxtx/wave.do
auk_sdsdi-v1.1/source
auk_sdsdi-v1.1/source/cyclone_board
auk_sdsdi-v1.1/source/cyclone_board/sdsdi_rxtx_cyclone_board.v
auk_sdsdi-v1.1/source/demo
auk_sdsdi-v1.1/source/demo/fifo_256x20.v
auk_sdsdi-v1.1/source/demo/freq_trans.v
auk_sdsdi-v1.1/source/demo/sclk_pll_x10.v
auk_sdsdi-v1.1/source/demo/sclk_pll_x30_4.v
auk_sdsdi-v1.1/source/demo/sclk_pll_x50_4.v
auk_sdsdi-v1.1/source/demo/sdsdi_io_interface.v
auk_sdsdi-v1.1/source/demo/sdsdi_rxtx.v
auk_sdsdi-v1.1/source/demo/sync.v
auk_sdsdi-v1.1/source/demoboard
auk_sdsdi-v1.1/source/demoboard/sdsdi_rxtx_demoboard.v
auk_sdsdi-v1.1/source/sdi_receive
auk_sdsdi-v1.1/source/sdi_receive/gxb_rxsample.v
auk_sdsdi-v1.1/source/sdi_receive/s2p.v
auk_sdsdi-v1.1/source/sdi_receive/sdi_aligner.v
auk_sdsdi-v1.1/source/sdi_receive/sdi_descrambler.v
auk_sdsdi-v1.1/source/sdi_receive/sdsdi_receive.v
auk_sdsdi-v1.1/source/sdi_transmit
auk_sdsdi-v1.1/source/sdi_transmit/gen_colorbar.v
auk_sdsdi-v1.1/source/sdi_transmit/gen_patho.v
auk_sdsdi-v1.1/source/sdi_transmit/p2s.v
auk_sdsdi-v1.1/source/sdi_transmit/pattern_gen.v
auk_sdsdi-v1.1/source/sdi_transmit/sdi_makeframe.v
auk_sdsdi-v1.1/source/sdi_transmit/sdi_scrambler.v
auk_sdsdi-v1.1/source_vhdl
auk_sdsdi-v1.1/source_vhdl/cyclone_board
auk_sdsdi-v1.1/source_vhdl/cyclone_board/sdsdi_rxtx_cyclone_board.vhd
auk_sdsdi-v1.1/source_vhdl/demo
auk_sdsdi-v1.1/source_vhdl/demo/fifo_256x20.vhd
auk_sdsdi-v1.1/source_vhdl/demo/freq_trans.vhd
auk_sdsdi-v1.1/source_vhdl/demo/sclk_pll_x10.vhd
auk_sdsdi-v1.1/source_vhdl/demo/sclk_pll_x30_4.vhd
auk_sdsdi-v1.1/source_vhdl/demo/sclk_pll_x50_4.vhd
auk_sdsdi-v1.1/source_vhdl/demo/sdsdi_io_interface.vhd
auk_sdsdi-v1.1/source_vhdl/demo/sdsdi_rxtx.vhd
auk_sdsdi-v1.1/source_vhdl/demo/sync.vhd
auk_sdsdi-v1.1/source_vhdl/demoboard
auk_sdsdi-v1.1/source_vhdl/demoboard/sdsdi_rxtx_demoboard.vhd
auk_sdsdi-v1.1/source_vhdl/lib
auk_sdsdi-v1.1/source_vhdl/lib/sdi_std_logic.vhd
auk_sdsdi-v1.1/source_vhdl/sdi_receive
auk_sdsdi-v1.1/source_vhdl/sdi_receive/gxb_rxsample.vhd
auk_sdsdi-v1.1/source_vhdl/sdi_receive/s2p.vhd
auk_sdsdi-v1.1/source_vhdl/sdi_receive/sdi_aligner.vhd
auk_sdsdi-v1.1/source_vhdl/sdi_receive/sdi_descrambler.vhd
auk_sdsdi-v1.1/source_vhdl/sdi_receive/sdsdi_receive.vhd
auk_sdsdi-v1.1/source_vhdl/sdi_transmit
auk_sdsdi-v1.1/source_vhdl/sdi_transmit/gen_colorbar.vhd
auk_sdsdi-v1.1/source_vhdl/sdi_transmit/gen_patho.vhd
auk_sdsdi-v1.1/source_vhdl/sdi_transmit/p2s.vhd
auk_sdsdi-v1.1/source_vhdl/sdi_transmit/pattern_gen.vhd
auk_sdsdi-v1.1/source_vhdl/sdi_transmit/sdi_makeframe.vhd
auk_sdsdi-v1.1/source_vhdl/sdi_transmit/sdi_scrambler.vhd
auk_sdsdi-v1.1/tb
auk_sdsdi-v1.1/tb/tb_sdsdi_rxtx.v

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