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文件名称:S6_VGA_change

  • 所属分类：
    Embeded-SCM Develop
  • 标签属性：
    [ASM] [源码]
  • 上传时间：
    2012-11-16
  • 文件大小：
    2.62mb
  • 已下载：
    0次
  • 提 供 者：
    wp***
  • 相关连接：
    无
  • 下载说明：
    别用迅雷下载，失败请重下，重下不扣分！
修正介绍说明

介绍说明－－下载内容来自于网络，使用问题请自行百度

利用cpld作为控制器实现驱动vga显示器，虽然只有8位色，但是实现方式只得借鉴，这个可以利用按键实现图片的相互切换-Used as a controller to achieve cpld drive vga display, although only 8-bit color, but the implementations are only for reference, this can be achieved using buttons to switch between images
相关搜索： vga cpld

(系统自动生成,下载前可以参看下载内容)

下载文件列表

S6_VGA_change/Src/ColorBar.bdf
S6_VGA_change/Src/ColorBar.bsf
S6_VGA_change/Src/vga_vl.v
S6_VGA_change/Src
S6_VGA_change/Proj/cmp_state.ini
S6_VGA_change/Proj/ColorBar.asm.rpt
S6_VGA_change/Proj/ColorBar.cdf
S6_VGA_change/Proj/ColorBar.done
S6_VGA_change/Proj/ColorBar.eda.rpt
S6_VGA_change/Proj/ColorBar.fit.eqn
S6_VGA_change/Proj/ColorBar.fit.rpt
S6_VGA_change/Proj/ColorBar.fit.summary
S6_VGA_change/Proj/ColorBar.flow.rpt
S6_VGA_change/Proj/ColorBar.map.eqn
S6_VGA_change/Proj/ColorBar.map.rpt
S6_VGA_change/Proj/ColorBar.map.summary
S6_VGA_change/Proj/ColorBar.mif
S6_VGA_change/Proj/ColorBar.pin
S6_VGA_change/Proj/ColorBar.pof
S6_VGA_change/Proj/ColorBar.qpf
S6_VGA_change/Proj/ColorBar.qsf
S6_VGA_change/Proj/ColorBar.qws
S6_VGA_change/Proj/ColorBar.sof
S6_VGA_change/Proj/ColorBar.tan.rpt
S6_VGA_change/Proj/ColorBar.tan.summary
S6_VGA_change/Proj/ColorBar_assignment_defaults.qdf
S6_VGA_change/Proj/rom.bsf
S6_VGA_change/Proj/rom.v
S6_VGA_change/Proj/rom_8.bsf
S6_VGA_change/Proj/rom_8.v
S6_VGA_change/Proj/rom_8_bb.v
S6_VGA_change/Proj/rom_bb.v
S6_VGA_change/Proj/stp1.stp
S6_VGA_change/Proj/VGA_PLL.bsf
S6_VGA_change/Proj/VGA_PLL.v
S6_VGA_change/Proj/VGA_PLL_bb.v
S6_VGA_change/Proj/vga_vl.bsf
S6_VGA_change/Proj/simulation/modelsim/ColorBar.vo
S6_VGA_change/Proj/simulation/modelsim/ColorBar_modelsim.xrf
S6_VGA_change/Proj/simulation/modelsim/ColorBar_v.sdo
S6_VGA_change/Proj/simulation/modelsim/cyclone_atoms.v
S6_VGA_change/Proj/simulation/modelsim/vga_test.cr.mti
S6_VGA_change/Proj/simulation/modelsim/vga_test.mpf
S6_VGA_change/Proj/simulation/modelsim/vga_test.v
S6_VGA_change/Proj/simulation/modelsim/vga_vl.v
S6_VGA_change/Proj/simulation/modelsim/vsim.wlf
S6_VGA_change/Proj/simulation/modelsim/wave.do
S6_VGA_change/Proj/simulation/modelsim/work/_info
S6_VGA_change/Proj/simulation/modelsim/work/vga_vl/verilog.asm
S6_VGA_change/Proj/simulation/modelsim/work/vga_vl/_primary.dat
S6_VGA_change/Proj/simulation/modelsim/work/vga_vl/_primary.vhd
S6_VGA_change/Proj/simulation/modelsim/work/vga_vl
S6_VGA_change/Proj/simulation/modelsim/work/vga_test/verilog.asm
S6_VGA_change/Proj/simulation/modelsim/work/vga_test/_primary.dat
S6_VGA_change/Proj/simulation/modelsim/work/vga_test/_primary.vhd
S6_VGA_change/Proj/simulation/modelsim/work/vga_test
S6_VGA_change/Proj/simulation/modelsim/work/cyclone_scale_cntr/verilog.asm
S6_VGA_change/Proj/simulation/modelsim/work/cyclone_scale_cntr/_primary.dat
S6_VGA_change/Proj/simulation/modelsim/work/cyclone_scale_cntr/_primary.vhd
S6_VGA_change/Proj/simulation/modelsim/work/cyclone_scale_cntr
S6_VGA_change/Proj/simulation/modelsim/work/cyclone_routing_wire/verilog.asm
S6_VGA_change/Proj/simulation/modelsim/work/cyclone_routing_wire/_primary.dat
S6_VGA_change/Proj/simulation/modelsim/work/cyclone_routing_wire/_primary.vhd
S6_VGA_change/Proj/simulation/modelsim/work/cyclone_routing_wire
S6_VGA_change/Proj/simulation/modelsim/work/cyclone_ram_register/verilog.asm
S6_VGA_change/Proj/simulation/modelsim/work/cyclone_ram_register/_primary.dat
S6_VGA_change/Proj/simulation/modelsim/work/cyclone_ram_register/_primary.vhd
S6_VGA_change/Proj/simulation/modelsim/work/cyclone_ram_register
S6_VGA_change/Proj/simulation/modelsim/work/cyclone_ram_pulse_generator/verilog.asm
S6_VGA_change/Proj/simulation/modelsim/work/cyclone_ram_pulse_generator/_primary.dat
S6_VGA_change/Proj/simulation/modelsim/work/cyclone_ram_pulse_generator/_primary.vhd
S6_VGA_change/Proj/simulation/modelsim/work/cyclone_ram_pulse_generator
S6_VGA_change/Proj/simulation/modelsim/work/cyclone_ram_block/verilog.asm
S6_VGA_change/Proj/simulation/modelsim/work/cyclone_ram_block/_primary.dat
S6_VGA_change/Proj/simulation/modelsim/work/cyclone_ram_block/_primary.vhd
S6_VGA_change/Proj/simulation/modelsim/work/cyclone_ram_block
S6_VGA_change/Proj/simulation/modelsim/work/cyclone_pll_reg/verilog.asm
S6_VGA_change/Proj/simulation/modelsim/work/cyclone_pll_reg/_primary.dat
S6_VGA_change/Proj/simulation/modelsim/work/cyclone_pll_reg/_primary.vhd
S6_VGA_change/Proj/simulation/modelsim/work/cyclone_pll_reg
S6_VGA_change/Proj/simulation/modelsim/work/cyclone_pll/verilog.asm
S6_VGA_change/Proj/simulation/modelsim/work/cyclone_pll/_primary.dat
S6_VGA_change/Proj/simulation/modelsim/work/cyclone_pll/_primary.vhd
S6_VGA_change/Proj/simulation/modelsim/work/cyclone_pll
S6_VGA_change/Proj/simulation/modelsim/work/cyclone_n_cntr/verilog.asm
S6_VGA_change/Proj/simulation/modelsim/work/cyclone_n_cntr/_primary.dat
S6_VGA_change/Proj/simulation/modelsim/work/cyclone_n_cntr/_primary.vhd
S6_VGA_change/Proj/simulation/modelsim/work/cyclone_n_cntr
S6_VGA_change/Proj/simulation/modelsim/work/cyclone_nmux21/verilog.asm
S6_VGA_change/Proj/simulation/modelsim/work/cyclone_nmux21/_primary.dat
S6_VGA_change/Proj/simulation/modelsim/work/cyclone_nmux21/_primary.vhd
S6_VGA_change/Proj/simulation/modelsim/work/cyclone_nmux21
S6_VGA_change/Proj/simulation/modelsim/work/cyclone_m_cntr/verilog.asm
S6_VGA_change/Proj/simulation/modelsim/work/cyclone_m_cntr/_primary.dat
S6_VGA_change/Proj/simulation/modelsim/work/cyclone_m_cntr/_primary.vhd
S6_VGA_change/Proj/simulation/modelsim/work/cyclon

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