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文件名称:ddr_verilog_xilinx
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- 上传时间:2012-11-16
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文件大小:663.16kb
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xilinx的ddr sdram控制器文档-xilinx of ddr sdram controller documentation
(系统自动生成,下载前可以参看下载内容)
下载文件列表
ddr_verilog_xilinx
ddr_verilog_xilinx/.recordref
ddr_verilog_xilinx/AutoConstraint_top.sdc
ddr_verilog_xilinx/backup
ddr_verilog_xilinx/compxlib.cfg
ddr_verilog_xilinx/coreip
ddr_verilog_xilinx/ddr_verilog_xilinx.ise
ddr_verilog_xilinx/ddr_verilog_xilinx.restore
ddr_verilog_xilinx/ddr_verilog_xilinx_xdb
ddr_verilog_xilinx/ddr_verilog_xilinx_xdb/tmp
ddr_verilog_xilinx/define.v
ddr_verilog_xilinx/doc
ddr_verilog_xilinx/doc/ddr_xilinx.pdf
ddr_verilog_xilinx/glbl.v
ddr_verilog_xilinx/model.list
ddr_verilog_xilinx/modelsim.ini
ddr_verilog_xilinx/mt46v4m16.v
ddr_verilog_xilinx/readme.txt
ddr_verilog_xilinx/rpt_top.areasrr
ddr_verilog_xilinx/rpt_top_areasrr.htm
ddr_verilog_xilinx/run_options.txt
ddr_verilog_xilinx/stdout.log
ddr_verilog_xilinx/string_decode_fn.v
ddr_verilog_xilinx/synplicity.ucf
ddr_verilog_xilinx/syntmp
ddr_verilog_xilinx/syntmp/sap.log
ddr_verilog_xilinx/syntmp/top.plg
ddr_verilog_xilinx/syntmp/top_flink.htm
ddr_verilog_xilinx/syntmp/top_srr.htm
ddr_verilog_xilinx/syntmp/top_toc.htm
ddr_verilog_xilinx/tb_top.v
ddr_verilog_xilinx/test.fdo
ddr_verilog_xilinx/test.udo
ddr_verilog_xilinx/test_wave.fdo
ddr_verilog_xilinx/top.edn
ddr_verilog_xilinx/top.fse
ddr_verilog_xilinx/top.htm
ddr_verilog_xilinx/top.map
ddr_verilog_xilinx/top.ncf
ddr_verilog_xilinx/top.prj
ddr_verilog_xilinx/top.sap
ddr_verilog_xilinx/top.sdc
ddr_verilog_xilinx/top.srd
ddr_verilog_xilinx/top.srm
ddr_verilog_xilinx/top.srr
ddr_verilog_xilinx/top.srs
ddr_verilog_xilinx/top.szr
ddr_verilog_xilinx/top.tlg
ddr_verilog_xilinx/top.ucf
ddr_verilog_xilinx/top_compile.tcl
ddr_verilog_xilinx/top_func.v
ddr_verilog_xilinx/top_map.tcl
ddr_verilog_xilinx/top_summary.html
ddr_verilog_xilinx/transcript
ddr_verilog_xilinx/traplog.tlg
ddr_verilog_xilinx/verif
ddr_verilog_xilinx/verif/top.vif
ddr_verilog_xilinx/vsim.wlf
ddr_verilog_xilinx/wave.do
ddr_verilog_xilinx/work
ddr_verilog_xilinx/work/addr_latch
ddr_verilog_xilinx/work/addr_latch/_primary.dat
ddr_verilog_xilinx/work/addr_latch/_primary.vhd
ddr_verilog_xilinx/work/brst_cntr
ddr_verilog_xilinx/work/brst_cntr/_primary.dat
ddr_verilog_xilinx/work/brst_cntr/_primary.vhd
ddr_verilog_xilinx/work/clk_dlls
ddr_verilog_xilinx/work/clk_dlls/_primary.dat
ddr_verilog_xilinx/work/clk_dlls/_primary.vhd
ddr_verilog_xilinx/work/controller
ddr_verilog_xilinx/work/controller/_primary.dat
ddr_verilog_xilinx/work/controller/_primary.vhd
ddr_verilog_xilinx/work/cslt_cntr
ddr_verilog_xilinx/work/cslt_cntr/_primary.dat
ddr_verilog_xilinx/work/cslt_cntr/_primary.vhd
ddr_verilog_xilinx/work/data_dly
ddr_verilog_xilinx/work/data_dly/_primary.dat
ddr_verilog_xilinx/work/data_dly/_primary.vhd
ddr_verilog_xilinx/work/data_path
ddr_verilog_xilinx/work/data_path/_primary.dat
ddr_verilog_xilinx/work/data_path/_primary.vhd
ddr_verilog_xilinx/work/ddr_ctlr
ddr_verilog_xilinx/work/ddr_ctlr/_primary.dat
ddr_verilog_xilinx/work/ddr_ctlr/_primary.vhd
ddr_verilog_xilinx/work/ddr_dq_io_16
ddr_verilog_xilinx/work/ddr_dq_io_16/_primary.dat
ddr_verilog_xilinx/work/ddr_dq_io_16/_primary.vhd
ddr_verilog_xilinx/work/ddr_iob_ff
ddr_verilog_xilinx/work/ddr_iob_ff/_primary.dat
ddr_verilog_xilinx/work/ddr_iob_ff/_primary.vhd
ddr_verilog_xilinx/work/glbl
ddr_verilog_xilinx/work/glbl/_primary.dat
ddr_verilog_xilinx/work/glbl/_primary.vhd
ddr_verilog_xilinx/work/mt46v4m16
ddr_verilog_xilinx/work/mt46v4m16/_primary.dat
ddr_verilog_xilinx/work/mt46v4m16/_primary.vhd
ddr_verilog_xilinx/work/rcd_cntr
ddr_verilog_xilinx/work/rcd_cntr/_primary.dat
ddr_verilog_xilinx/work/rcd_cntr/_primary.vhd
ddr_verilog_xilinx/work/test
ddr_verilog_xilinx/work/test/_primary.dat
ddr_verilog_xilinx/work/test/_primary.vhd
ddr_verilog_xilinx/work/top
ddr_verilog_xilinx/work/top/_primary.dat
ddr_verilog_xilinx/work/top/_primary.vhd
ddr_verilog_xilinx/work/user_int
ddr_verilog_xilinx/work/user_int/_primary.dat
ddr_verilog_xilinx/work/user_int/_primary.vhd
ddr_verilog_xilinx/work/_info
ddr_verilog_xilinx/work/_opt
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ddr_verilog_xilinx/work/_opt/D__Xilinx_10.1_ISE_verilog_mti_se_unisims_ver_@b@u@f@g_fast.dt2
ddr_verilog_xilinx/work/_opt/D__Xilinx_10.1_ISE_verilog_mti_se_unisims_ver_@c@l@k@d@l@l_fast.asm
ddr_verilog_xilinx/work/_opt/D__Xilinx_10.1_ISE_verilog_mti_se_unisims_ver_@c@l@k@d@l@l_fast.dt2
ddr_verilog_xilinx/work/_opt/D__Xilinx_10.1_ISE_verilog_mti_se_unisims_ver_@f@d@d@r@r@s@e_fast.asm
ddr_verilog_xilinx/work/_opt/D__Xilinx_10.1_ISE_verilog_mti_se_unisims_ver_@f@d@d@r@r@s@e_fast.dt2
ddr_verilog_xilinx/work/_opt/D__Xilinx_10.1_ISE_verilog_mti_se_unisims_ver_@f@d_fast.asm
ddr_verilog_xilinx/work/_opt/D__Xilinx_10.1_ISE_verilog_mti_se_unisims_ver_@f@d_fast.dt2
ddr_verilog_xilinx/work/_opt/D__Xilinx_10.1_ISE_verilog_mti_se_unisims_ver_@i@b@u@f@g_fast.dt2
ddr_verilog_xilinx/work/_opt/D__Xilinx_10.1_ISE_verilog_mti_se_unisims_ver_@i@b@u@f_fast.dt2
ddr_verilog_xilinx/work/_opt/D__Xilinx_10.1_ISE_verilog_mti_se_unisims_ver_@i@o@b@u@f_fast.dt2
ddr_verilog_xilinx/work/_opt/D__Xilinx_10.1_ISE_verilog_mti_se_unisims_ver_@o@b@u@f@t_fast
ddr_verilog_xilinx/.recordref
ddr_verilog_xilinx/AutoConstraint_top.sdc
ddr_verilog_xilinx/backup
ddr_verilog_xilinx/compxlib.cfg
ddr_verilog_xilinx/coreip
ddr_verilog_xilinx/ddr_verilog_xilinx.ise
ddr_verilog_xilinx/ddr_verilog_xilinx.restore
ddr_verilog_xilinx/ddr_verilog_xilinx_xdb
ddr_verilog_xilinx/ddr_verilog_xilinx_xdb/tmp
ddr_verilog_xilinx/define.v
ddr_verilog_xilinx/doc
ddr_verilog_xilinx/doc/ddr_xilinx.pdf
ddr_verilog_xilinx/glbl.v
ddr_verilog_xilinx/model.list
ddr_verilog_xilinx/modelsim.ini
ddr_verilog_xilinx/mt46v4m16.v
ddr_verilog_xilinx/readme.txt
ddr_verilog_xilinx/rpt_top.areasrr
ddr_verilog_xilinx/rpt_top_areasrr.htm
ddr_verilog_xilinx/run_options.txt
ddr_verilog_xilinx/stdout.log
ddr_verilog_xilinx/string_decode_fn.v
ddr_verilog_xilinx/synplicity.ucf
ddr_verilog_xilinx/syntmp
ddr_verilog_xilinx/syntmp/sap.log
ddr_verilog_xilinx/syntmp/top.plg
ddr_verilog_xilinx/syntmp/top_flink.htm
ddr_verilog_xilinx/syntmp/top_srr.htm
ddr_verilog_xilinx/syntmp/top_toc.htm
ddr_verilog_xilinx/tb_top.v
ddr_verilog_xilinx/test.fdo
ddr_verilog_xilinx/test.udo
ddr_verilog_xilinx/test_wave.fdo
ddr_verilog_xilinx/top.edn
ddr_verilog_xilinx/top.fse
ddr_verilog_xilinx/top.htm
ddr_verilog_xilinx/top.map
ddr_verilog_xilinx/top.ncf
ddr_verilog_xilinx/top.prj
ddr_verilog_xilinx/top.sap
ddr_verilog_xilinx/top.sdc
ddr_verilog_xilinx/top.srd
ddr_verilog_xilinx/top.srm
ddr_verilog_xilinx/top.srr
ddr_verilog_xilinx/top.srs
ddr_verilog_xilinx/top.szr
ddr_verilog_xilinx/top.tlg
ddr_verilog_xilinx/top.ucf
ddr_verilog_xilinx/top_compile.tcl
ddr_verilog_xilinx/top_func.v
ddr_verilog_xilinx/top_map.tcl
ddr_verilog_xilinx/top_summary.html
ddr_verilog_xilinx/transcript
ddr_verilog_xilinx/traplog.tlg
ddr_verilog_xilinx/verif
ddr_verilog_xilinx/verif/top.vif
ddr_verilog_xilinx/vsim.wlf
ddr_verilog_xilinx/wave.do
ddr_verilog_xilinx/work
ddr_verilog_xilinx/work/addr_latch
ddr_verilog_xilinx/work/addr_latch/_primary.dat
ddr_verilog_xilinx/work/addr_latch/_primary.vhd
ddr_verilog_xilinx/work/brst_cntr
ddr_verilog_xilinx/work/brst_cntr/_primary.dat
ddr_verilog_xilinx/work/brst_cntr/_primary.vhd
ddr_verilog_xilinx/work/clk_dlls
ddr_verilog_xilinx/work/clk_dlls/_primary.dat
ddr_verilog_xilinx/work/clk_dlls/_primary.vhd
ddr_verilog_xilinx/work/controller
ddr_verilog_xilinx/work/controller/_primary.dat
ddr_verilog_xilinx/work/controller/_primary.vhd
ddr_verilog_xilinx/work/cslt_cntr
ddr_verilog_xilinx/work/cslt_cntr/_primary.dat
ddr_verilog_xilinx/work/cslt_cntr/_primary.vhd
ddr_verilog_xilinx/work/data_dly
ddr_verilog_xilinx/work/data_dly/_primary.dat
ddr_verilog_xilinx/work/data_dly/_primary.vhd
ddr_verilog_xilinx/work/data_path
ddr_verilog_xilinx/work/data_path/_primary.dat
ddr_verilog_xilinx/work/data_path/_primary.vhd
ddr_verilog_xilinx/work/ddr_ctlr
ddr_verilog_xilinx/work/ddr_ctlr/_primary.dat
ddr_verilog_xilinx/work/ddr_ctlr/_primary.vhd
ddr_verilog_xilinx/work/ddr_dq_io_16
ddr_verilog_xilinx/work/ddr_dq_io_16/_primary.dat
ddr_verilog_xilinx/work/ddr_dq_io_16/_primary.vhd
ddr_verilog_xilinx/work/ddr_iob_ff
ddr_verilog_xilinx/work/ddr_iob_ff/_primary.dat
ddr_verilog_xilinx/work/ddr_iob_ff/_primary.vhd
ddr_verilog_xilinx/work/glbl
ddr_verilog_xilinx/work/glbl/_primary.dat
ddr_verilog_xilinx/work/glbl/_primary.vhd
ddr_verilog_xilinx/work/mt46v4m16
ddr_verilog_xilinx/work/mt46v4m16/_primary.dat
ddr_verilog_xilinx/work/mt46v4m16/_primary.vhd
ddr_verilog_xilinx/work/rcd_cntr
ddr_verilog_xilinx/work/rcd_cntr/_primary.dat
ddr_verilog_xilinx/work/rcd_cntr/_primary.vhd
ddr_verilog_xilinx/work/test
ddr_verilog_xilinx/work/test/_primary.dat
ddr_verilog_xilinx/work/test/_primary.vhd
ddr_verilog_xilinx/work/top
ddr_verilog_xilinx/work/top/_primary.dat
ddr_verilog_xilinx/work/top/_primary.vhd
ddr_verilog_xilinx/work/user_int
ddr_verilog_xilinx/work/user_int/_primary.dat
ddr_verilog_xilinx/work/user_int/_primary.vhd
ddr_verilog_xilinx/work/_info
ddr_verilog_xilinx/work/_opt
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ddr_verilog_xilinx/work/_opt/D__Xilinx_10.1_ISE_verilog_mti_se_unimacro_ver__info
ddr_verilog_xilinx/work/_opt/D__Xilinx_10.1_ISE_verilog_mti_se_unisims_ver_@b@u@f@g_fast.dt2
ddr_verilog_xilinx/work/_opt/D__Xilinx_10.1_ISE_verilog_mti_se_unisims_ver_@c@l@k@d@l@l_fast.asm
ddr_verilog_xilinx/work/_opt/D__Xilinx_10.1_ISE_verilog_mti_se_unisims_ver_@c@l@k@d@l@l_fast.dt2
ddr_verilog_xilinx/work/_opt/D__Xilinx_10.1_ISE_verilog_mti_se_unisims_ver_@f@d@d@r@r@s@e_fast.asm
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ddr_verilog_xilinx/work/_opt/D__Xilinx_10.1_ISE_verilog_mti_se_unisims_ver_@f@d_fast.asm
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ddr_verilog_xilinx/work/_opt/D__Xilinx_10.1_ISE_verilog_mti_se_unisims_ver_@i@b@u@f_fast.dt2
ddr_verilog_xilinx/work/_opt/D__Xilinx_10.1_ISE_verilog_mti_se_unisims_ver_@i@o@b@u@f_fast.dt2
ddr_verilog_xilinx/work/_opt/D__Xilinx_10.1_ISE_verilog_mti_se_unisims_ver_@o@b@u@f@t_fast
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