文件名称:wb_dma
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- 上传时间:2012-11-16
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文件大小:140.1kb
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已下载:0次
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wishbone接口dma控制器,适合于构建soc系统,特别适用于视频开发-dma controller with wishbone interface,fitting for soc design,especially for video development.
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下载文件列表
wb_dma/syn/bin/comp.dc
wb_dma/syn/bin/design_spec.dc
wb_dma/syn/bin/lib_spec.dc
wb_dma/syn/bin/read.dc
wb_dma/syn/bin
wb_dma/syn
wb_dma/sim/rtl_sim/bin/Makefile
wb_dma/sim/rtl_sim/bin
wb_dma/sim/rtl_sim
wb_dma/sim
wb_dma/rtl/verilog/wb_dma_ch_arb.v
wb_dma/rtl/verilog/wb_dma_ch_pri_enc.v
wb_dma/rtl/verilog/wb_dma_ch_rf.v
wb_dma/rtl/verilog/wb_dma_ch_sel.v
wb_dma/rtl/verilog/wb_dma_de.v
wb_dma/rtl/verilog/wb_dma_defines.v
wb_dma/rtl/verilog/wb_dma_inc30r.v
wb_dma/rtl/verilog/wb_dma_pri_enc_sub.v
wb_dma/rtl/verilog/wb_dma_rf.v
wb_dma/rtl/verilog/wb_dma_top.v
wb_dma/rtl/verilog/wb_dma_wb_if.v
wb_dma/rtl/verilog/wb_dma_wb_mast.v
wb_dma/rtl/verilog/wb_dma_wb_slv.v
wb_dma/rtl/verilog
wb_dma/rtl
wb_dma/doc/dma_doc.pdf
wb_dma/doc/README.txt
wb_dma/doc/STATUS.txt
wb_dma/doc
wb_dma/bench/verilog/tests.v
wb_dma/bench/verilog/test_bench_top.v
wb_dma/bench/verilog/wb_mast_model.v
wb_dma/bench/verilog/wb_model_defines.v
wb_dma/bench/verilog/wb_slv_model.v
wb_dma/bench/verilog
wb_dma/bench
wb_dma
wb_dma/syn/bin/design_spec.dc
wb_dma/syn/bin/lib_spec.dc
wb_dma/syn/bin/read.dc
wb_dma/syn/bin
wb_dma/syn
wb_dma/sim/rtl_sim/bin/Makefile
wb_dma/sim/rtl_sim/bin
wb_dma/sim/rtl_sim
wb_dma/sim
wb_dma/rtl/verilog/wb_dma_ch_arb.v
wb_dma/rtl/verilog/wb_dma_ch_pri_enc.v
wb_dma/rtl/verilog/wb_dma_ch_rf.v
wb_dma/rtl/verilog/wb_dma_ch_sel.v
wb_dma/rtl/verilog/wb_dma_de.v
wb_dma/rtl/verilog/wb_dma_defines.v
wb_dma/rtl/verilog/wb_dma_inc30r.v
wb_dma/rtl/verilog/wb_dma_pri_enc_sub.v
wb_dma/rtl/verilog/wb_dma_rf.v
wb_dma/rtl/verilog/wb_dma_top.v
wb_dma/rtl/verilog/wb_dma_wb_if.v
wb_dma/rtl/verilog/wb_dma_wb_mast.v
wb_dma/rtl/verilog/wb_dma_wb_slv.v
wb_dma/rtl/verilog
wb_dma/rtl
wb_dma/doc/dma_doc.pdf
wb_dma/doc/README.txt
wb_dma/doc/STATUS.txt
wb_dma/doc
wb_dma/bench/verilog/tests.v
wb_dma/bench/verilog/test_bench_top.v
wb_dma/bench/verilog/wb_mast_model.v
wb_dma/bench/verilog/wb_model_defines.v
wb_dma/bench/verilog/wb_slv_model.v
wb_dma/bench/verilog
wb_dma/bench
wb_dma
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