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文件名称:s_UIC_v3.03.tar

  • 所属分类：
    VHDL-FPGA-Verilog
  • 标签属性：
    [PDF]
  • 上传时间：
    2012-11-16
  • 文件大小：
    2.52mb
  • 已下载：
    0次
  • 提 供 者：
    cur****
  • 相关连接：
    无
  • 下载说明：
    别用迅雷下载，失败请重下，重下不扣分！
修正介绍说明

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(IBM) Interrupter Controller for PowePC405 (verilog)
相关搜索： optical encoder interrupter

(系统自动生成,下载前可以参看下载内容)

下载文件列表

s_UIC_v3.03/
s_UIC_v3.03/UIC.README
s_UIC_v3.03/synthesis/
s_UIC_v3.03/synthesis/UIC.con.tcl
s_UIC_v3.03/synthesis/UIC.synopsys.tcl
s_UIC_v3.03/synthesis/.synopsys_dc.setup
s_UIC_v3.03/synthesis/scan/
s_UIC_v3.03/synthesis/scan/UIC.con.tcl
s_UIC_v3.03/synthesis/scan/UIC.synopsys.tcl
s_UIC_v3.03/synthesis/scan/UIC.scan.tcl
s_UIC_v3.03/synthesis/scan/UIC.stil
s_UIC_v3.03/synthesis/scan/command.log
s_UIC_v3.03/synthesis/scan/UIC.db.justcompiled
s_UIC_v3.03/synthesis/scan/UIC.db.withscan
s_UIC_v3.03/synthesis/scan/design.log
s_UIC_v3.03/synthesis/scan/UIC.scanable.db
s_UIC_v3.03/synthesis/scan/Reference.log
s_UIC_v3.03/synthesis/scan/REPORT.log
s_UIC_v3.03/synthesis/scan/UIC.slog
s_UIC_v3.03/synthesis/scan/UIC.mapped.v
s_UIC_v3.03/synthesis/scan/UIC.mapped.db
s_UIC_v3.03/synthesis/scan/work/
s_UIC_v3.03/synthesis/scan/work/reg_gatedC1_ungatedC2-verilog.pvl
s_UIC_v3.03/synthesis/scan/work/REG_GATEDC1_UNGATEDC2.mr
s_UIC_v3.03/synthesis/scan/work/reg_ungatedC1_gatedC2-verilog.pvl
s_UIC_v3.03/synthesis/scan/work/REG_UNGATEDC1_GATEDC2.mr
s_UIC_v3.03/synthesis/scan/work/reg_ungatedC1_ungatedC2-verilog.pvl
s_UIC_v3.03/synthesis/scan/work/REG_UNGATEDC1_UNGATEDC2.mr
s_UIC_v3.03/synthesis/scan/work/reg_ungatedC1_ungatedC2_enable-verilog.pvl
s_UIC_v3.03/synthesis/scan/work/REG_UNGATEDC1_UNGATEDC2_ENABLE.mr
s_UIC_v3.03/synthesis/scan/work/reg_dff_busclocks-verilog.pvl
s_UIC_v3.03/synthesis/scan/work/REG_DFF_BUSCLOCKS.mr
s_UIC_v3.03/synthesis/scan/work/rcvr-verilog.pvl
s_UIC_v3.03/synthesis/scan/work/RCVR.mr
s_UIC_v3.03/synthesis/scan/work/uic_mac-verilog.pvl
s_UIC_v3.03/synthesis/scan/work/UIC_MAC.mr
s_UIC_v3.03/synthesis/scan/work/UIC-verilog.pvl
s_UIC_v3.03/synthesis/scan/work/UIC.mr
s_UIC_v3.03/primetime/
s_UIC_v3.03/primetime/UIC.primetime.tcl
s_UIC_v3.03/primetime/UIC.con.tcl
s_UIC_v3.03/doc/
s_UIC_v3.03/doc/uic_bk7-22-02.pdf
s_UIC_v3.03/doc/s_UIC_addendum.pdf
s_UIC_v3.03/rtl_src/
s_UIC_v3.03/rtl_src/UIC.syn.v
s_UIC_v3.03/rtl_src/UIC.definitions.v
s_UIC_v3.03/formality/
s_UIC_v3.03/formality/rtl_vs_synNet/
s_UIC_v3.03/formality/rtl_vs_synNet/UIC.formality.tcl
s_UIC_v3.03/formality/rtl_vs_synNet/UIC.formality.scan.tcl
s_UIC_v3.03/formality/rtl_vs_synNet/xav.log
s_UIC_v3.03/formality/rtl_vs_synNet/formality.log
s_UIC_v3.03/formality/rtl_vs_synNet/fm_shell_command.log
s_UIC_v3.03/formality/rtl_vs_synNet/UIC.failingpts.rpt
s_UIC_v3.03/formality/rtl_vs_synNet/UIC.abortedpts.rpt
s_UIC_v3.03/formality/rtl_vs_synNet/UIC.unmatched.rpt
s_UIC_v3.03/formality/rtl_vs_synNet/UIC.candidates.rpt
s_UIC_v3.03/formality/rtl_vs_synNet/UIC.passingpts.rpt
s_UIC_v3.03/formality/rtl_vs_synNet/UIC.comparepts.rpt
s_UIC_v3.03/vcd/
s_UIC_v3.03/vcd/UIC.vcd
s_UIC_v3.03/synthesis_cu11/
s_UIC_v3.03/synthesis_cu11/UIC.con.tcl
s_UIC_v3.03/synthesis_cu11/UIC.synopsys.tcl
s_UIC_v3.03/synthesis_cu11/.synopsys_dc.setup
s_UIC_v3.03/synthesis_cu11/scan/
s_UIC_v3.03/synthesis_cu11/scan/UIC.con.tcl
s_UIC_v3.03/synthesis_cu11/scan/UIC.synopsys.tcl
s_UIC_v3.03/synthesis_cu11/scan/UIC.scan.tcl
s_UIC_v3.03/synthesis_cu11/scan/UIC.stil
s_UIC_v3.03/synthesis_cu11/scan/command.log
s_UIC_v3.03/synthesis_cu11/scan/UIC.db.justcompiled
s_UIC_v3.03/synthesis_cu11/scan/UIC.db.withscan
s_UIC_v3.03/synthesis_cu11/scan/design.log
s_UIC_v3.03/synthesis_cu11/scan/UIC.scanable.db
s_UIC_v3.03/synthesis_cu11/scan/Reference.log
s_UIC_v3.03/synthesis_cu11/scan/REPORT.log
s_UIC_v3.03/synthesis_cu11/scan/UIC.slog
s_UIC_v3.03/synthesis_cu11/scan/UIC.mapped.v
s_UIC_v3.03/synthesis_cu11/scan/UIC.mapped.db
s_UIC_v3.03/synthesis_cu11/scan/work/
s_UIC_v3.03/synthesis_cu11/scan/work/reg_gatedC1_ungatedC2-verilog.pvl
s_UIC_v3.03/synthesis_cu11/scan/work/REG_GATEDC1_UNGATEDC2.mr
s_UIC_v3.03/synthesis_cu11/scan/work/reg_ungatedC1_gatedC2-verilog.pvl
s_UIC_v3.03/synthesis_cu11/scan/work/REG_UNGATEDC1_GATEDC2.mr
s_UIC_v3.03/synthesis_cu11/scan/work/reg_ungatedC1_ungatedC2-verilog.pvl
s_UIC_v3.03/synthesis_cu11/scan/work/REG_UNGATEDC1_UNGATEDC2.mr
s_UIC_v3.03/synthesis_cu11/scan/work/reg_ungatedC1_ungatedC2_enable-verilog.pvl
s_UIC_v3.03/synthesis_cu11/scan/work/REG_UNGATEDC1_UNGATEDC2_ENABLE.mr
s_UIC_v3.03/synthesis_cu11/scan/work/reg_dff_busclocks-verilog.pvl
s_UIC_v3.03/synthesis_cu11/scan/work/REG_DFF_BUSCLOCKS.mr
s_UIC_v3.03/synthesis_cu11/scan/work/rcvr-verilog.pvl
s_UIC_v3.03/synthesis_cu11/scan/work/RCVR.mr
s_UIC_v3.03/synthesis_cu11/scan/work/uic_mac-verilog.pvl
s_UIC_v3.03/synthesis_cu11/scan/work/UIC_MAC.mr
s_UIC_v3.03/synthesis_cu11/scan/work/UIC-verilog.pvl
s_UIC_v3.03/synthesis_cu11/scan/work/UIC.mr
s_UIC_v3.03/testbench/
s_UIC_v3.03/testbench/UIC_testbench.v
s_UIC_v3.03/testbench/UIC_monitor.v
s_UIC_v3.03/testbench/UIC.do
s_UIC_v3.03/testbench/UIC.vsim
s_UIC_v3.03/testbench/UIC.xl
s_UIC_v3.03/testbench/UIC.nc
s_UIC_v3.03/testbench/UIC.vcs
s_UIC_v3.03/testbench/README.UIC.testbench
s_UIC_v3.03/testbench/UIC_stim.v

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