CS有效后的最初1.5至2个转换周期内,ADS7816采样输入信号,此时输出引脚Dout呈三态,

DCL K的第2个下降沿后,Dout使能并输出一个时钟周期的低电平的无效信号,在随后的12个

DCL K周期中,Dout输出转换结果,其输出数据的格式是最高有效位(B11位)在前,当最低有效

位(B0位)输出后,若CS变为高电位,则一次转换结束,最高转换速度200kHz-CS valid after the first 1.5 to 2 conversion cycle, ADS7816 sampling the input signal, this time three-state output pin Dout was, DCL K after the first two falling, Dout enable and outputs a clock cycle of low invalid signal, in the next 12 DCL K cycle, Dout output conversion results, the output data format is the most significant bit (B11-bit) in the former, when the least significant bit (B0-bit) output, if the CS becomes high potential, then the end of a conversion, the maximum conversion rate of 200kHz