文件名称:cml
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基于Verilog的数字基带通信系统
3. 项目描述：本系统为通信原理课程设计课题之一，用Verilog语言编写数字基带通信系统的应用程序，完成P=31的m序列的生成，并进行HDB3编码传输，在接收端进行译码接收。-Verilog-based digital baseband communication system 3. Project Descr iption: The system is one of the topics Communication Theory course design, using Verilog language digital baseband communication system applications, the completion of P = 31 m-sequence generation, and make HDB3 coded transmission, reception at the receiving end for decoding.
3. 项目描述：本系统为通信原理课程设计课题之一，用Verilog语言编写数字基带通信系统的应用程序，完成P=31的m序列的生成，并进行HDB3编码传输，在接收端进行译码接收。-Verilog-based digital baseband communication system 3. Project Descr iption: The system is one of the topics Communication Theory course design, using Verilog language digital baseband communication system applications, the completion of P = 31 m-sequence generation, and make HDB3 coded transmission, reception at the receiving end for decoding.
相关搜索： 数字基带
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下载文件列表
add_b.bsf
add_b.v
add_v.bsf
add_v.v
clock.bsf
clock.v
cml.asm.rpt
cml.bdf
cml.done
cml.fit.eqn
cml.fit.rpt
cml.fit.smsg
cml.fit.summary
cml.flow.rpt
cml.map.eqn
cml.map.rpt
cml.map.summary
cml.pin
cml.qpf
cml.qsf
cml.qws
cml.sim.rpt
cml.tan.rpt
cml.tan.summary
cml.vwf
cml_assignment_defaults.qdf
polar.bsf
polar.v
seqdet.bsf
seqdet.v
yima.bsf
yima.v
db/prev_cmp_cml.qmsg
db/cml.map.qmsg
db/cml.eco.cdb
db/cml.sld_design_entry.sci
db/cml.cbx.xml
db/cml.hif
db/cml.(0).cnf.cdb
db/cml.(0).cnf.hdb
db/cml.(1).cnf.cdb
db/cml.(1).cnf.hdb
db/cml.(2).cnf.cdb
db/cml.(2).cnf.hdb
db/cml.(3).cnf.cdb
db/cml.(3).cnf.hdb
db/cml.(4).cnf.cdb
db/cml.(4).cnf.hdb
db/cml.(5).cnf.cdb
db/cml.(5).cnf.hdb
db/cml.(6).cnf.cdb
db/cml.(6).cnf.hdb
db/cml.hier_info
db/cml.rtlv_sg_swap.cdb
db/cml.pre_map.hdb
db/cml.rtlv.hdb
db/cml.pre_map.cdb
db/cml.map.logdb
db/cml.psp
db/cml.pss
db/cml.dbp
db/cml.cmp.rdb
db/cml.sgdiff.hdb
db/cml.fit.qmsg
db/cml.cmp.logdb
db/cml.asm.qmsg
db/cml.syn_hier_info
db/cml.cmp0.ddb
db/cml.map.cdb
db/cml.sim.qmsg
db/cml.cmp.hdb
db/cml.rtlv_sg.cdb
db/cml.map.hdb
db/cml.tan.qmsg
db/cml.sim.cvwf
db/cml.sim.rdb
db/cml.sim.vwf
db/cml.sim.hdb
db/prev_cmp_cml.map.qmsg
db/prev_cmp_cml.sim.qmsg
db/cml.sgdiff.cdb
db/cml.cmp.cdb
db/cml.db_info
db/prev_cmp_cml.fit.qmsg
db/prev_cmp_cml.asm.qmsg
db/cml.cmp.tdb
db/prev_cmp_cml.tan.qmsg
db/cml.sld_design_entry_dsc.sci
db/cml.tis_db_list.ddb
db/cml.signalprobe.cdb
db/cml.eds_overflow
db/wed.wsf
db
add_b.v
add_v.bsf
add_v.v
clock.bsf
clock.v
cml.asm.rpt
cml.bdf
cml.done
cml.fit.eqn
cml.fit.rpt
cml.fit.smsg
cml.fit.summary
cml.flow.rpt
cml.map.eqn
cml.map.rpt
cml.map.summary
cml.pin
cml.qpf
cml.qsf
cml.qws
cml.sim.rpt
cml.tan.rpt
cml.tan.summary
cml.vwf
cml_assignment_defaults.qdf
polar.bsf
polar.v
seqdet.bsf
seqdet.v
yima.bsf
yima.v
db/prev_cmp_cml.qmsg
db/cml.map.qmsg
db/cml.eco.cdb
db/cml.sld_design_entry.sci
db/cml.cbx.xml
db/cml.hif
db/cml.(0).cnf.cdb
db/cml.(0).cnf.hdb
db/cml.(1).cnf.cdb
db/cml.(1).cnf.hdb
db/cml.(2).cnf.cdb
db/cml.(2).cnf.hdb
db/cml.(3).cnf.cdb
db/cml.(3).cnf.hdb
db/cml.(4).cnf.cdb
db/cml.(4).cnf.hdb
db/cml.(5).cnf.cdb
db/cml.(5).cnf.hdb
db/cml.(6).cnf.cdb
db/cml.(6).cnf.hdb
db/cml.hier_info
db/cml.rtlv_sg_swap.cdb
db/cml.pre_map.hdb
db/cml.rtlv.hdb
db/cml.pre_map.cdb
db/cml.map.logdb
db/cml.psp
db/cml.pss
db/cml.dbp
db/cml.cmp.rdb
db/cml.sgdiff.hdb
db/cml.fit.qmsg
db/cml.cmp.logdb
db/cml.asm.qmsg
db/cml.syn_hier_info
db/cml.cmp0.ddb
db/cml.map.cdb
db/cml.sim.qmsg
db/cml.cmp.hdb
db/cml.rtlv_sg.cdb
db/cml.map.hdb
db/cml.tan.qmsg
db/cml.sim.cvwf
db/cml.sim.rdb
db/cml.sim.vwf
db/cml.sim.hdb
db/prev_cmp_cml.map.qmsg
db/prev_cmp_cml.sim.qmsg
db/cml.sgdiff.cdb
db/cml.cmp.cdb
db/cml.db_info
db/prev_cmp_cml.fit.qmsg
db/prev_cmp_cml.asm.qmsg
db/cml.cmp.tdb
db/prev_cmp_cml.tan.qmsg
db/cml.sld_design_entry_dsc.sci
db/cml.tis_db_list.ddb
db/cml.signalprobe.cdb
db/cml.eds_overflow
db/wed.wsf
db
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