文件名称:74hc4017
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- 上传时间:2012-11-16
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IC VHDL集成设计
IC VHDL集成设计-IC VHDL design
IC VHDL集成设计-IC VHDL design
(系统自动生成,下载前可以参看下载内容)
下载文件列表
74hc4017.pdf
74hc4017/
74hc4017/4017_module.prj
74hc4017/component/
74hc4017/constraint/
74hc4017/coreconsole/
74hc4017/designer/
74hc4017/designer/impl1/
74hc4017/designer/impl1/4017model.ide_des
74hc4017/designer/impl1/4017_module.ide_des
74hc4017/designer/impl1/designer.log
74hc4017/designer/impl1/designer_synth_check.log
74hc4017/designer/impl1/model.ide_des
74hc4017/designer/impl1/model4017.adb
74hc4017/designer/impl1/model4017.dtf/
74hc4017/designer/impl1/model4017.dtf/verify.log
74hc4017/designer/impl1/model4017.ide_des
74hc4017/designer/impl1/model4017.pdb
74hc4017/designer/impl1/model4017.pdb.depends
74hc4017/designer/impl1/model4017.tcl
74hc4017/designer/impl1/model4017_ba.sdf
74hc4017/designer/impl1/model4017_ba.sdf_max.csd
74hc4017/designer/impl1/model4017_ba.v
74hc4017/designer/impl1/model4017_fp/
74hc4017/designer/impl1/model4017_fp/$$FlashPro_FPBBALTLPT1.L$$
74hc4017/designer/impl1/model4017_fp/model4017.log
74hc4017/designer/impl1/model4017_fp/model4017.pro
74hc4017/designer/impl1/model4017_fp/projectData/
74hc4017/designer/impl1/model4017_fp/projectData/model4017.pdb
74hc4017/designer/impl1/simulation/
74hc4017/designer/impl1/simulation/postlayout/
74hc4017/designer/impl1/simulation/postlayout/model4017/
74hc4017/designer/impl1/simulation/postlayout/model4017/verilog.psm
74hc4017/designer/impl1/simulation/postlayout/model4017/_primary.dat
74hc4017/designer/impl1/simulation/postlayout/model4017/_primary.dbs
74hc4017/designer/impl1/simulation/postlayout/model4017/_primary.vhd
74hc4017/designer/impl1/simulation/postlayout/stimulus/
74hc4017/designer/impl1/simulation/postlayout/stimulus/verilog.psm
74hc4017/designer/impl1/simulation/postlayout/stimulus/_primary.dat
74hc4017/designer/impl1/simulation/postlayout/stimulus/_primary.dbs
74hc4017/designer/impl1/simulation/postlayout/stimulus/_primary.vhd
74hc4017/designer/impl1/simulation/postlayout/tb_clock_minmax/
74hc4017/designer/impl1/simulation/postlayout/tb_clock_minmax/verilog.psm
74hc4017/designer/impl1/simulation/postlayout/tb_clock_minmax/_primary.dat
74hc4017/designer/impl1/simulation/postlayout/tb_clock_minmax/_primary.dbs
74hc4017/designer/impl1/simulation/postlayout/tb_clock_minmax/_primary.vhd
74hc4017/designer/impl1/simulation/postlayout/testbench/
74hc4017/designer/impl1/simulation/postlayout/testbench/verilog.psm
74hc4017/designer/impl1/simulation/postlayout/testbench/_primary.dat
74hc4017/designer/impl1/simulation/postlayout/testbench/_primary.dbs
74hc4017/designer/impl1/simulation/postlayout/testbench/_primary.vhd
74hc4017/designer/impl1/simulation/postlayout/_info
74hc4017/designer/impl1/simulation/postlayout/_temp/
74hc4017/designer/impl1/simulation/postlayout/_vmake
74hc4017/hdl/
74hc4017/hdl/4017_module.v
74hc4017/phy_synthesis/
74hc4017/simulation/
74hc4017/simulation/modelsim.ini
74hc4017/simulation/modelsim.ini.sav
74hc4017/simulation/modelsim.log
74hc4017/simulation/postsynth/
74hc4017/simulation/postsynth/model4017/
74hc4017/simulation/postsynth/model4017/verilog.psm
74hc4017/simulation/postsynth/model4017/_primary.dat
74hc4017/simulation/postsynth/model4017/_primary.dbs
74hc4017/simulation/postsynth/model4017/_primary.vhd
74hc4017/simulation/postsynth/stimulus/
74hc4017/simulation/postsynth/stimulus/verilog.psm
74hc4017/simulation/postsynth/stimulus/_primary.dat
74hc4017/simulation/postsynth/stimulus/_primary.dbs
74hc4017/simulation/postsynth/stimulus/_primary.vhd
74hc4017/simulation/postsynth/tb_clock_minmax/
74hc4017/simulation/postsynth/tb_clock_minmax/verilog.psm
74hc4017/simulation/postsynth/tb_clock_minmax/_primary.dat
74hc4017/simulation/postsynth/tb_clock_minmax/_primary.dbs
74hc4017/simulation/postsynth/tb_clock_minmax/_primary.vhd
74hc4017/simulation/postsynth/testbench/
74hc4017/simulation/postsynth/testbench/verilog.psm
74hc4017/simulation/postsynth/testbench/_primary.dat
74hc4017/simulation/postsynth/testbench/_primary.dbs
74hc4017/simulation/postsynth/testbench/_primary.vhd
74hc4017/simulation/postsynth/_info
74hc4017/simulation/postsynth/_temp/
74hc4017/simulation/postsynth/_vmake
74hc4017/simulation/presynth/
74hc4017/simulation/presynth/model/
74hc4017/simulation/presynth/model/verilog.psm
74hc4017/simulation/presynth/model/_primary.dat
74hc4017/simulation/presynth/model/_primary.dbs
74hc4017/simulation/presynth/model/_primary.vhd
74hc4017/simulation/presynth/model4017/
74hc4017/simulation/presynth/model4017/verilog.psm
74hc4017/simulation/presynth/model4017/_primary.dat
74hc4017/simulation/presynth/model4017/_primary.dbs
74hc4017/simulation/presynth/model4017/_primary.vhd
74hc4017/simulation/presynth/stimulus/
74hc4017/simulation/presynth/stimulus/verilog.psm
74hc4017/simulation/presynth/stimulus/_primary.dat
74hc4017/simulation/presynth/stimulus/_primary.dbs
74hc4017/simulation/presynth/stimulus/_primary.vhd
74hc4017/simulation/presynth/tb_clock_minmax/
74hc4017/simulation/presynth/tb_clock_minmax/verilog.psm
74hc4017/simulation/presynth/tb_clock_minmax/_primary.dat
74hc4017/simulation/presynth/tb_clock_minmax/_primary.dbs
74hc4017/simulation/presynth/tb_clock_minmax/_primary.vhd
74hc4017/simulation/presynth/testbench/
74hc4017/
74hc4017/4017_module.prj
74hc4017/component/
74hc4017/constraint/
74hc4017/coreconsole/
74hc4017/designer/
74hc4017/designer/impl1/
74hc4017/designer/impl1/4017model.ide_des
74hc4017/designer/impl1/4017_module.ide_des
74hc4017/designer/impl1/designer.log
74hc4017/designer/impl1/designer_synth_check.log
74hc4017/designer/impl1/model.ide_des
74hc4017/designer/impl1/model4017.adb
74hc4017/designer/impl1/model4017.dtf/
74hc4017/designer/impl1/model4017.dtf/verify.log
74hc4017/designer/impl1/model4017.ide_des
74hc4017/designer/impl1/model4017.pdb
74hc4017/designer/impl1/model4017.pdb.depends
74hc4017/designer/impl1/model4017.tcl
74hc4017/designer/impl1/model4017_ba.sdf
74hc4017/designer/impl1/model4017_ba.sdf_max.csd
74hc4017/designer/impl1/model4017_ba.v
74hc4017/designer/impl1/model4017_fp/
74hc4017/designer/impl1/model4017_fp/$$FlashPro_FPBBALTLPT1.L$$
74hc4017/designer/impl1/model4017_fp/model4017.log
74hc4017/designer/impl1/model4017_fp/model4017.pro
74hc4017/designer/impl1/model4017_fp/projectData/
74hc4017/designer/impl1/model4017_fp/projectData/model4017.pdb
74hc4017/designer/impl1/simulation/
74hc4017/designer/impl1/simulation/postlayout/
74hc4017/designer/impl1/simulation/postlayout/model4017/
74hc4017/designer/impl1/simulation/postlayout/model4017/verilog.psm
74hc4017/designer/impl1/simulation/postlayout/model4017/_primary.dat
74hc4017/designer/impl1/simulation/postlayout/model4017/_primary.dbs
74hc4017/designer/impl1/simulation/postlayout/model4017/_primary.vhd
74hc4017/designer/impl1/simulation/postlayout/stimulus/
74hc4017/designer/impl1/simulation/postlayout/stimulus/verilog.psm
74hc4017/designer/impl1/simulation/postlayout/stimulus/_primary.dat
74hc4017/designer/impl1/simulation/postlayout/stimulus/_primary.dbs
74hc4017/designer/impl1/simulation/postlayout/stimulus/_primary.vhd
74hc4017/designer/impl1/simulation/postlayout/tb_clock_minmax/
74hc4017/designer/impl1/simulation/postlayout/tb_clock_minmax/verilog.psm
74hc4017/designer/impl1/simulation/postlayout/tb_clock_minmax/_primary.dat
74hc4017/designer/impl1/simulation/postlayout/tb_clock_minmax/_primary.dbs
74hc4017/designer/impl1/simulation/postlayout/tb_clock_minmax/_primary.vhd
74hc4017/designer/impl1/simulation/postlayout/testbench/
74hc4017/designer/impl1/simulation/postlayout/testbench/verilog.psm
74hc4017/designer/impl1/simulation/postlayout/testbench/_primary.dat
74hc4017/designer/impl1/simulation/postlayout/testbench/_primary.dbs
74hc4017/designer/impl1/simulation/postlayout/testbench/_primary.vhd
74hc4017/designer/impl1/simulation/postlayout/_info
74hc4017/designer/impl1/simulation/postlayout/_temp/
74hc4017/designer/impl1/simulation/postlayout/_vmake
74hc4017/hdl/
74hc4017/hdl/4017_module.v
74hc4017/phy_synthesis/
74hc4017/simulation/
74hc4017/simulation/modelsim.ini
74hc4017/simulation/modelsim.ini.sav
74hc4017/simulation/modelsim.log
74hc4017/simulation/postsynth/
74hc4017/simulation/postsynth/model4017/
74hc4017/simulation/postsynth/model4017/verilog.psm
74hc4017/simulation/postsynth/model4017/_primary.dat
74hc4017/simulation/postsynth/model4017/_primary.dbs
74hc4017/simulation/postsynth/model4017/_primary.vhd
74hc4017/simulation/postsynth/stimulus/
74hc4017/simulation/postsynth/stimulus/verilog.psm
74hc4017/simulation/postsynth/stimulus/_primary.dat
74hc4017/simulation/postsynth/stimulus/_primary.dbs
74hc4017/simulation/postsynth/stimulus/_primary.vhd
74hc4017/simulation/postsynth/tb_clock_minmax/
74hc4017/simulation/postsynth/tb_clock_minmax/verilog.psm
74hc4017/simulation/postsynth/tb_clock_minmax/_primary.dat
74hc4017/simulation/postsynth/tb_clock_minmax/_primary.dbs
74hc4017/simulation/postsynth/tb_clock_minmax/_primary.vhd
74hc4017/simulation/postsynth/testbench/
74hc4017/simulation/postsynth/testbench/verilog.psm
74hc4017/simulation/postsynth/testbench/_primary.dat
74hc4017/simulation/postsynth/testbench/_primary.dbs
74hc4017/simulation/postsynth/testbench/_primary.vhd
74hc4017/simulation/postsynth/_info
74hc4017/simulation/postsynth/_temp/
74hc4017/simulation/postsynth/_vmake
74hc4017/simulation/presynth/
74hc4017/simulation/presynth/model/
74hc4017/simulation/presynth/model/verilog.psm
74hc4017/simulation/presynth/model/_primary.dat
74hc4017/simulation/presynth/model/_primary.dbs
74hc4017/simulation/presynth/model/_primary.vhd
74hc4017/simulation/presynth/model4017/
74hc4017/simulation/presynth/model4017/verilog.psm
74hc4017/simulation/presynth/model4017/_primary.dat
74hc4017/simulation/presynth/model4017/_primary.dbs
74hc4017/simulation/presynth/model4017/_primary.vhd
74hc4017/simulation/presynth/stimulus/
74hc4017/simulation/presynth/stimulus/verilog.psm
74hc4017/simulation/presynth/stimulus/_primary.dat
74hc4017/simulation/presynth/stimulus/_primary.dbs
74hc4017/simulation/presynth/stimulus/_primary.vhd
74hc4017/simulation/presynth/tb_clock_minmax/
74hc4017/simulation/presynth/tb_clock_minmax/verilog.psm
74hc4017/simulation/presynth/tb_clock_minmax/_primary.dat
74hc4017/simulation/presynth/tb_clock_minmax/_primary.dbs
74hc4017/simulation/presynth/tb_clock_minmax/_primary.vhd
74hc4017/simulation/presynth/testbench/
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