文件名称:74hc85
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- 上传时间:2012-11-16
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文件大小:361.97kb
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IC VHDL 集成设计
IC VHDL 集成设计-IC VHDL design
IC VHDL 集成设计-IC VHDL design
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下载文件列表
74hc85.pdf
74hc85/
74hc85/74hc85.prj
74hc85/component/
74hc85/constraint/
74hc85/coreconsole/
74hc85/designer/
74hc85/designer/impl1/
74hc85/designer/impl1/compar4.ide_des
74hc85/designer/impl1/compare4.adb
74hc85/designer/impl1/compare4.dtf/
74hc85/designer/impl1/compare4.dtf/verify.log
74hc85/designer/impl1/compare4.ide_des
74hc85/designer/impl1/compare4.pdb
74hc85/designer/impl1/compare4.pdb.depends
74hc85/designer/impl1/compare4.tcl
74hc85/designer/impl1/compare4_fp/
74hc85/designer/impl1/compare4_fp/$$FlashPro_07294.L$$
74hc85/designer/impl1/compare4_fp/compare4.log
74hc85/designer/impl1/compare4_fp/compare4.pro
74hc85/designer/impl1/compare4_fp/projectData/
74hc85/designer/impl1/compare4_fp/projectData/compare4.pdb
74hc85/designer/impl1/designer.log
74hc85/designer/impl1/simulation/
74hc85/hdl/
74hc85/hdl/74hc85.v
74hc85/phy_synthesis/
74hc85/simulation/
74hc85/simulation/modelsim.ini
74hc85/simulation/modelsim.ini.sav
74hc85/simulation/modelsim.log
74hc85/simulation/presynth/
74hc85/simulation/presynth/compar4/
74hc85/simulation/presynth/compar4/verilog.psm
74hc85/simulation/presynth/compar4/_primary.dat
74hc85/simulation/presynth/compar4/_primary.dbs
74hc85/simulation/presynth/compar4/_primary.vhd
74hc85/simulation/presynth/compare4/
74hc85/simulation/presynth/compare4/verilog.psm
74hc85/simulation/presynth/compare4/_primary.dat
74hc85/simulation/presynth/compare4/_primary.dbs
74hc85/simulation/presynth/compare4/_primary.vhd
74hc85/simulation/presynth/testbench/
74hc85/simulation/presynth/testbench/verilog.psm
74hc85/simulation/presynth/testbench/_primary.dat
74hc85/simulation/presynth/testbench/_primary.dbs
74hc85/simulation/presynth/testbench/_primary.vhd
74hc85/simulation/presynth/_info
74hc85/simulation/presynth/_temp/
74hc85/simulation/run.do
74hc85/simulation/vsim.wlf
74hc85/smartgen/
74hc85/smartgen/smartgen.aws
74hc85/stimulus/
74hc85/stimulus/testbench.v
74hc85/synthesis/
74hc85/synthesis/.recordref
74hc85/synthesis/backup/
74hc85/synthesis/compare4.areasrr
74hc85/synthesis/compare4.edn
74hc85/synthesis/compare4.fse
74hc85/synthesis/compare4.htm
74hc85/synthesis/compare4.map
74hc85/synthesis/compare4.pdc
74hc85/synthesis/compare4.sap
74hc85/synthesis/compare4.sdf
74hc85/synthesis/compare4.so
74hc85/synthesis/compare4.srd
74hc85/synthesis/compare4.srm
74hc85/synthesis/compare4.srr
74hc85/synthesis/compare4.srs
74hc85/synthesis/compare4.szr
74hc85/synthesis/compare4.tlg
74hc85/synthesis/compare4_sdc.sdc
74hc85/synthesis/compare4_syn.prj
74hc85/synthesis/coreip/
74hc85/synthesis/run_options.txt
74hc85/synthesis/stdout.log
74hc85/synthesis/syntmp/
74hc85/synthesis/syntmp/compare4.plg
74hc85/synthesis/syntmp/compare4_flink.htm
74hc85/synthesis/syntmp/compare4_srr.htm
74hc85/synthesis/syntmp/compare4_toc.htm
74hc85/synthesis/syntmp/sap.log
74hc85/synthesis/traplog.tlg
74hc85/viewdraw/
74hc85/viewdraw/sch/
74hc85/viewdraw/sym/
74hc85/viewdraw/vf/
74hc85/viewdraw/vf/project.lst
74hc85/viewdraw/viewdraw.ini
74hc85/viewdraw/wir/
74hc85/
74hc85/74hc85.prj
74hc85/component/
74hc85/constraint/
74hc85/coreconsole/
74hc85/designer/
74hc85/designer/impl1/
74hc85/designer/impl1/compar4.ide_des
74hc85/designer/impl1/compare4.adb
74hc85/designer/impl1/compare4.dtf/
74hc85/designer/impl1/compare4.dtf/verify.log
74hc85/designer/impl1/compare4.ide_des
74hc85/designer/impl1/compare4.pdb
74hc85/designer/impl1/compare4.pdb.depends
74hc85/designer/impl1/compare4.tcl
74hc85/designer/impl1/compare4_fp/
74hc85/designer/impl1/compare4_fp/$$FlashPro_07294.L$$
74hc85/designer/impl1/compare4_fp/compare4.log
74hc85/designer/impl1/compare4_fp/compare4.pro
74hc85/designer/impl1/compare4_fp/projectData/
74hc85/designer/impl1/compare4_fp/projectData/compare4.pdb
74hc85/designer/impl1/designer.log
74hc85/designer/impl1/simulation/
74hc85/hdl/
74hc85/hdl/74hc85.v
74hc85/phy_synthesis/
74hc85/simulation/
74hc85/simulation/modelsim.ini
74hc85/simulation/modelsim.ini.sav
74hc85/simulation/modelsim.log
74hc85/simulation/presynth/
74hc85/simulation/presynth/compar4/
74hc85/simulation/presynth/compar4/verilog.psm
74hc85/simulation/presynth/compar4/_primary.dat
74hc85/simulation/presynth/compar4/_primary.dbs
74hc85/simulation/presynth/compar4/_primary.vhd
74hc85/simulation/presynth/compare4/
74hc85/simulation/presynth/compare4/verilog.psm
74hc85/simulation/presynth/compare4/_primary.dat
74hc85/simulation/presynth/compare4/_primary.dbs
74hc85/simulation/presynth/compare4/_primary.vhd
74hc85/simulation/presynth/testbench/
74hc85/simulation/presynth/testbench/verilog.psm
74hc85/simulation/presynth/testbench/_primary.dat
74hc85/simulation/presynth/testbench/_primary.dbs
74hc85/simulation/presynth/testbench/_primary.vhd
74hc85/simulation/presynth/_info
74hc85/simulation/presynth/_temp/
74hc85/simulation/run.do
74hc85/simulation/vsim.wlf
74hc85/smartgen/
74hc85/smartgen/smartgen.aws
74hc85/stimulus/
74hc85/stimulus/testbench.v
74hc85/synthesis/
74hc85/synthesis/.recordref
74hc85/synthesis/backup/
74hc85/synthesis/compare4.areasrr
74hc85/synthesis/compare4.edn
74hc85/synthesis/compare4.fse
74hc85/synthesis/compare4.htm
74hc85/synthesis/compare4.map
74hc85/synthesis/compare4.pdc
74hc85/synthesis/compare4.sap
74hc85/synthesis/compare4.sdf
74hc85/synthesis/compare4.so
74hc85/synthesis/compare4.srd
74hc85/synthesis/compare4.srm
74hc85/synthesis/compare4.srr
74hc85/synthesis/compare4.srs
74hc85/synthesis/compare4.szr
74hc85/synthesis/compare4.tlg
74hc85/synthesis/compare4_sdc.sdc
74hc85/synthesis/compare4_syn.prj
74hc85/synthesis/coreip/
74hc85/synthesis/run_options.txt
74hc85/synthesis/stdout.log
74hc85/synthesis/syntmp/
74hc85/synthesis/syntmp/compare4.plg
74hc85/synthesis/syntmp/compare4_flink.htm
74hc85/synthesis/syntmp/compare4_srr.htm
74hc85/synthesis/syntmp/compare4_toc.htm
74hc85/synthesis/syntmp/sap.log
74hc85/synthesis/traplog.tlg
74hc85/viewdraw/
74hc85/viewdraw/sch/
74hc85/viewdraw/sym/
74hc85/viewdraw/vf/
74hc85/viewdraw/vf/project.lst
74hc85/viewdraw/viewdraw.ini
74hc85/viewdraw/wir/
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