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mux16
- 在乘法器电路中，乘数中的每一位都要和被乘数的每一位相与，并产生其相应的乘积位。这些局部乘积要馈入到全加器的阵列中（合适的时候也可以用半加器），同时加法器向左移位并表示出乘法结果。-On time-multiplier circuit, in each of the multiplier to each BeiChengShu paleotopography, and produce its corresponding product bits. These local product will
add_tree
- 8*8乘法器 采用树形结构，如有不足之处请指正-8* 8 multiplier with tree structure, please correct me if inadequate
multplier-VerilogHDL
- 利用VerilogHDL语言编写的各种各样的乘法器，比如并列乘法器，省时乘法器等-VerilogHDL language using a variety of multipliers, such as parallel multipliers, multiplier and other time-saving
Multiplier
- 时序乘法器，verilog编写，速度慢，但消耗资源少，时钟沿到来时，输入/输出1bit数据-Sequential multiplier, verilog written, slow, but consume fewer resources, the clock edge arrives, the input/output 1bit data
MULTIPLIER
- 基于VHDL硬件描述语言设计的乘法器，位数可以修改-VHDL hardware descr iption language based on the design of the multiplier, the median can be modified
add_2x32_v1
- 2*32乘法器设计，只是部分Booth乘法器的设计，相关的后面部分将在需要时陆续上传。-design of an 2*32Multiplier
TLC7524FPGAchengxu
- TLC7524四象限乘法器用FPGA控制程序，该程序没有任何问题大家可以放心下载-TLC7524 four-quadrant multiplier using FPGA control program, the program does not download any question we can be assured
multiply_shift_add
- 基于移位相加运算的乘法器设计，multiply_shift_add中包含了完整的设计工程文件，可在Xilinx ISE中运行-Adding operation based on shift on time-multiplier design, multiply_shift_add contains the complete design engineering documents, Xilinx ISE in running
4X
- VHDL实现的4位乘法器，绝对好用，libero8.5仿真没问题！-VHDL implementation of the 4-bit multiplier
FPGASquare-RootRaised-CosineFilter
- 数字通信系统中, 基带信号的频谱一般较宽, 因此 传递前需对信号进行成形处理, 以改善其频谱特性,使 得在消除码间干扰与达到最佳检测接收的前提下,提高信道的频带利用率。目前,数字系统中常使用的波形成形滤波器有平方根升余弦滤波器、 高斯滤波器等。设计方法有卷积法或查表法, 其中: 卷积法的实现,需要消耗大量的乘法器与加法器,以构成具有一定延时的流水线结构。为降低硬件消耗,文献提出了一种分-FPGA Implementation of Square Root Raised Cosine Pu
mul
- 8×8乘法器的veilog代码，分几个模块书写，代码都在里面-8 × 8 multiplier veilog code in several modules written in code inside
Multiplier
- VHDL语言设计的乘法器，经过试验箱测试通过，用试验箱的8个拨码开关输入数字，按键按下输出结果。-VHDL language design of multiplier, after chamber test, with the chamber of the 8 DIP switch input numbers, key press output.
eda
- 这是我们平时做的EDA实验，包括加法器，乘法器，以及状态机等-This is what we usually do the EDA experiments, including adders, multipliers, and the state machine, etc.
chengfaqi
- 基于FPGA采用时序逻辑方法设计的16位乘法器代码-FPGA-based temporal logic designed using 16-bit multiplier code
VHDL-based-8-bit-multiplier
- 基于VHDL的8位乘法器运算程序，运用移位迭代法运算得出-VHDL-based 8-bit multiplier operation procedures, the use of shift operations derived iterative method
ga
- 电路演化，可以生成一个两位乘两位的乘法器-Circuits have evolved to generate a two by two multipliers
ECC
- 一种并行的有限域乘法器结构，用于ECC系统构建，多项式基-A parallel Finite Field Multiplier Architecture for ECC system construction, polynomial basis
multiplier
- 压缩的乘法器。是基于VERILOG 语言实现的，有较快的速度。-Compression of the multiplier. Is based on the VERILOG language, there is a faster speed.
myfir
- fir滤波器的源代码 基于乘法器结构的线性相位滤波器-The source code for fir filter structures based on linear phase filter multiplier
carry-save-multiplier-Verilog-code
- 进位存储乘法器Verilog代码,该乘法器的显著特点是其性能取决于使用的硬件而与数据长度无关.-carry save multiplier Verilog code