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chengfaqi
- 通过verilog hdl语言实现伽罗华域GF(q)乘法器设计-By verilog hdl language Galois field GF (q) Multiplier
SUANSHUJISUAN
- 通过verilog hdl实现加法器乘法器,除法器的设计-Achieved through verilog hdl adder multiplier, divider design
VHDL-
- 8位相等比较器,布斯乘法器,以为寄存器的VHDL实现-Eight for phase comparator, Booth multiplier, that registers of VHDL
multiplying-unit
- FPGA/CPLD开发,基于VHDL语言的乘法器的实现,数码管显示-FPGA/CPLD development, based on the realization of VHDL language multipliers, digital display
booth-16_16-multiplier
- 由verilog编写的利用booth编码的16*16有符号乘法器的代码,没有pipeline-a 16*16 multiplier with booth coding by verilog
verilog-codes-for-booth2
- 由verilog编写的采用booth2编码的16*16乘法器-a 16*16 multiplier with booth2 coding by verilog
chengfaqi
- 基于fpga的乘法器设计 已经验证请放心下载-Fpga-based multiplier design has been verified, please rest assured download
Ex3_4
- 两个16位整数相乘,乘积总是“向左增长”,这意味着多次相乘后乘积将会很快超出定点器件的数据范围。而且要将32位乘积保存到数据存储器,就要开销2个机器周期以及2个字的程序和RAM单元;并且,由于乘法器都是16位相乘,因此很难在后续的递推运算中,将32位乘积作为乘法器的输入。然而,小数相乘,乘积总是“向右增长”,这就使得超出定点器件数据范围的是我们不太感兴趣的部分。在小数乘法下,既可以存储32位乘积,也可以存储高16位乘积,这就允许用较少的资源保存结果,也便于用于递推运算中。这就是为什么定点DSP芯
mux16
- 十六位乘法器的verilog hdl 实现 及 modelsim 仿真 环境为quartusii9.0 自动调用modelsim 6.5输出仿真结果-fpga verilog hdl modelsim quartusii 16-bit multiplier
mux4booth
- fpga 使用verilog hdl 语言,quartusii 9.0编程环境,使用2booth算法设计的4bit乘法器。可以扩展为16bit乘法器。-fpga verilog hdl ,quartusii 9.0 ,2booth 4bit
multt
- 该程序实现了一个16*16的乘法器,可以用作设计乘法器参考-The program implements a 16* 16 multiplier, multiplier design can be used as reference
4BITMUIT
- 利用LPM_MUIT宏模块设计一个四位数据乘法器-Use LPM_MUIT macro module design a four data Multiplier
MSP430F5438_example
- MSP430F5430例程,包括AD采集模块、时钟模块、乘法器、定时器、串口、看门狗等模块底层驱动源码 -MSP430F5430 routines, including driver source code of AD collection module, clock module, multiplier, timer, serial port, and watchdog module etc.
leijiaqi
- verilog 语言描述的累加器和乘法器-verilog code
ddc
- 数字下变频模块,顶层文件奇偶抽取,还有乘法器-Digital down conversion modules, top file parity extraction, there is a multiplier
Hardware_Multiplier
- 利用MSP430F149内部的硬件乘法器进行8bit-8bit,16bit-16bit的乘法,只需三个主时钟周期,即可读出运算结果。-Using MSP430F149 internal hardware multiplier for 8bit-8bit, 16bit-16bit multiplication, just three master clock cycles, you can read out the result of the operation.
Chapter-2
- 3.1加法树乘法器add_tree_mult设计实例, 3.2查找表乘法器lookup_mult设计实例. 3.3布尔乘法器booth_mult设计实例 3.4移位除法器shift_divider设计实例 -3.1 adder tree multiplier add_tree_mult design example, 3.2 lookup table multiplier lookup_mult design examples. 3.3 Design Example 3.4 Bo
Chapter-3
- 3.1加法树乘法器add_tree_mult设计实例 3.2查找表乘法器lookup_mult设计实例 3.3布尔乘法器booth_mult设计实例 3.4移位除法器shift_divider设计实例-3.1 adder tree multiplier add_tree_mult design example 3.2 multiplier lookup_mult lookup table design example 3.3 Design Example 3.4 Boolean mu
Chapter-5
- 5.2 16位乘法器状态机实现 5.3 交通控制灯控制设计 5.4 PCI总线目标接口状态机设计-5.2 16 5.3 multiplier state machine traffic light control design 5.4 PCI bus target interface state machine design
N-bits-by-M-bits
- 这是一个verilog代码实现的常用乘法器。设计的是通用N比特乘M比特的二进制乘法器-This is a common multiplier verilog code. Design of a generic N bits by M bits of the binary multiplier