搜索资源列表
PLL
- 该测试程序用过Verilog HDL实现对PLL的分频，既频率管理功能-The Verilog HDL test procedure used to achieve the sub PLL frequency, only the frequency management function
div
- 这是一个基于CPLD的VHDL语言的分频例程-This is a CPLD-based crossover routine VHDL language
fpq
- 基于VHDL硬件描述语言的分频器的仿真实例与操作步骤-VHDL hardware descr iption language based on the divider of the simulation and the steps
tone.
- 这是一个八音盒数字系统。里面包括八音盒的自动演奏模块，数控分频模块，音节发生器，还有整体描述。-This is a music box digital system. Which includes an automatic music box playing the module, CNC frequency module, the syllable generator, as well as the overall descr iption.
H9
- 本实验利用8253做定时器，用定时器输出的脉冲控制8259产生中断 在8259中断处理程序中，对时、分、秒进行计数，在等待中断的循 环中用LED显示时间。 8253用定时器/计数器1，8253片选接CS4，地址为0C000H。8253时钟 源CLK1接分频电路的F/64输出。分频器的Fin接4MHz时钟。8253的 GATE1接VCC。 8259中断INT0接8253的OUT1，片选接CS5，地址为0D000H。 -useing 8255 and 8253
H25
- 本实验用8253做定时器输出音频信号，控制喇叭发出声音 将8253的CLK1接到1MHz脉冲信号上（1MHz信号可由4MHz信号 分频后得到），GATE1接VCC，OUT1接喇叭的脉冲输入。-useing the chip of 8253 to control the loudspeaker
VHDL
- 基于VHDL的分频器,程序源代码中完成对时钟信号CLK的2分频，4分频，8分频，16分频。-The frequency of an points based on VHDL program
71357135-serial-program
- 7135源程序，串行接法,晶振6M，四分之一分频-7135 serial program
Distributer
- VHDL编写的分频器。用于将50MHz的时钟脉冲分频成一个500Hz的扫描时钟和1Hz的秒脉冲。与我的其它8个模块配套构成一个数字钟。-Programmed with VHDL.A clock distributer which generates a 500Hz scaning clock and a 1Hz second impulse. It is one of my total 9 modules that are used to design a digital clock.
GetKey
- cpld的按键处理，偶数分数，奇数分频，小数分频-cpld key handling, even scores the odd frequency, fractional-N
980811872shukongfenpinqi
- 数控分频程序，改变其中的参数，实现所需要的品路-fen pin cheng xu
skfp
- EDA 16位数控分频，比较好地演示数控分频-EDA 16 位 digital divide, the better to demonstrate numerical frequency
vhdl
- vhdl的防抖模块 led灯 分频 跑马灯 键控等几个源程序-vhdl image stabilization module led light frequency shift keying, and several other source Marquee
Clk50M_div_1HZ
- Clk50M_div_1HZ，调试已通过，采用计数器分频 此实验采用计数器，将板载的50MHz时钟源分频为1Hz，分频的结果以LED灯的形式显示。下载电路至FPGA后，会发现LED0会以1Hz的频率闪动。-Clk50M_div_1HZ, using counter this study, frequency counter, onboard 50MHz clock frequency of 1Hz, frequency results in the form of LED lights di
DIV16
- DIV在编程中又叫做整除，即只得商的整数。DIV16实现16位的整除，一般用在分频。-DIV in the programming, also known as divisible, that' s only an integer. DIV16 to achieve 16-bit divides, usually used in frequency.
frequency5x2
- frequency5x2实现频率的分频，5*2即实现10分频，主要用于满足有些控制类的频率时钟。-frequency5x2 realize the frequency divider, 5* 2 frequency of achieving 10 points, mainly used to control the class to meet some of the frequency of the clock.
cpld
- 用FPGA实现简易数字示波器，分频，触发，以及，计数-FPGA implementation using simple digital oscilloscope, frequency, trigger, and, counting
CLK_3DIV
- 分频模块的设计 三分频 要求占空比为50-The design of the module frequency division three points of frequency requirements than empty for 50
counter100
- 本程序采用VHDL代码，在FPGA上实现100M分频的功能-failed to translate
sine
- 采用FPGA存储正弦波的256个点，分别输出，可以产生较好的正弦波，如果要产生其他的频率，只需改变分频比即可，即num的值。已经通过实物验证-FPGA-stored sine wave of 256 points, respectively, output, can produce a good sine wave, if you want to generate other frequencies, only Divider ratio can be changed, that value