搜索资源列表
vhdl-digital
- VHD L数字钟 设计源码 包括 设计思想 设计模块 -VHD L source, including digital clock design design design module
shuzizhong
- 山东省多个环节 发的芙蓉突入扼抗 数字钟设计 -Many areas of Shandong Province, digital clock design
shuzizhong
- 基于vhdl的具备闹钟提醒的多功能数字钟设计与应用-The alarm clock to remind vhdl-based multi-functional digital clock design and application
digital-clock-based-on-FPGA
- 基于FPGA的数字钟设计,编程语言是VHDL,编程环境是Quartus-digital clock based on FPGA
sep3203
- 基于sep3203的多功能数字钟设计,功能包括实时时钟显示,闹钟,矩阵键盘设置时钟和闹钟,报时,TFT真彩LCD液晶显示等等,由ADS1.2编译-Sep3203-based multi-functional digital clock features include real-time clock, alarm clock, matrix keyboard to set the clock and alarm clock, timer, TFT LCD LCD ADS1.2 compiled
5.1-PCF8563
- 基于pcf8563的数字钟设计,erilog语言编写,以调试-digital clock based on erilog langrage
clock1
- VHDL语言实现多功能数字钟设计:(1) 计时功能:这是本计时器设计的基本功能,每隔一分钟计时一次,并在显示屏上显示当前时间。 (2) 闹钟功能:如果当前时间与设置的闹钟时间相同,则扬声器发出蜂鸣声。 (3) 设置新的计时器时间:用户用数字键‘0’~‘9’输入新的时间,然后按 "TIME"键确认。 (4) 设置新的闹钟时间:用户用数字键“0”~“9”输入新的时间,然后按“ALARM”键确认。过程与(3)类似。 (5) 显示所设置的闹钟时间:在正常计时显示状态下,用户直接
duodiandingshishuzizhongsheji
- 多点定时数字钟设计,为实现一简易时钟的功能,需要用到单片机的定时器功能-More time a digital clock design for the realization of the function of a simple clock, need to use single chip microcomputer timer function
EDA1
- 用VHDL编程实现序列信号发生器与检测器设计和数字钟设计-VHDL programming sequence signal generator and detector design and the design of the digital clock
mian
- 实现数字钟设计,有四个按键可调整时间,按键是用中断实现,符合设计要求-Digital clock, there are four keys to adjust the time, the key is interrupted, meet the design requirements
vhdl2
- 不错的数字钟设计教程,自己照着编写了一边,好使啊!-Good tutorial digital clock design their own written according to the side, so that ah!
shuzhizhong(vhdl)
- 数字钟设计 计时计数器用24进制计时电路; 可手动校时,能分别进行时、分的校正; 整点报时; 选做:可设置闹时功能,当计时计到预定时间时,扬声器发出闹铃信号,闹铃时间为4s,并可提前终止闹铃。-Digital clock design
ep1c12_15_clock
- 数字钟设计:该程序完成了在Quartus Ⅱ上使用VHDL语言实现的24小时数字钟设计-Digital clock design: the process is complete Quartus Ⅱ a digital clock using VHDL language design
sch-clock
- 数字钟设计电路原理图高清 数字钟设计电路原理图高清-Digital clock to design the circuit diagram, hd
clock1
- 基于FPGA的数字钟设计代码,可显示时间,报时,调时,在开发板EP3C16Q240C8上可实现。-FPGA-based digital clock design code, time, timekeeping, tune in development board EP3C16Q240C8, to achieve.
CPLD-digital-clock-design
- 基于CPLD实验板的多功能数字钟设计,运用VHDL编写程序-Multifunction digital clock design based on CPLD experimental board, the use of VHDL programming
PIC16F877A-digital-clock-design
- 基于PIC16F877A的多功能数字钟设计,运用C语言设计程序-Use of the C language design program based on the design of multi-functional digital clock PIC16F877A
clock
- 数字钟设计,完整的代码,适合初学者,完整的数字钟功能,verilog语言-verilog clock design ,fuction is really well .
digital-clock
- 非常完善的数字钟设计,仅仅用单片机的定时器实现,可供学习单片机入门使用。-a quite perfect digital clock design,It is implemented by a timer only
shuzizhong
- 基于单片机下的数字钟设计,内含有DSN工程文件和论文,编程源码-Based on single-chip digital clock design contains the the DSN project file and papers, programming source code