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shuzuzhong
- 基于单片机51的数字钟设计,内容包括完整程序和仿真,以及根据设计过程写好的实验报告,可以参考-Digital clock design based on single-chip 51 includes complete program and simulation, as well as written lab report according to the design process, you can refer to
7279
- 基于HD7279A的数字钟设计 包含汇编和C代码-Based HD7279A digital clock design includes assembler and C code
Digital-clock-design
- 数字钟设计 用VHDL实现一个50MHZ到1HZ的分频器,利用Quartus II进行文本编辑输入和仿真硬件测试。实现一个60进制和24进制的计数器。测试成功。-Digital clock design using VHDL a 50MHZ to 1HZ divider using Quartus II simulation for text input and editing hardware test. Achieve a 60 hex and 24 hex counter. Test wa
shuzizhongsheji
- 有用的数字钟设计文档,有秒表、闹钟等模块,希望对大家有用!-JUST LEARN FROM IT!!ENJOY!
lab3_clock_20120520
- 基于ise的多功能数字钟设计。适用于basys2开发板-Ise-based multi-functional digital clock design
VHDL_LCD1602
- 基于fpga的万年历和数字钟设计,利用1602显示-Digital clock and calendar design based on fpga, using 1602 shows
data_clock
- 基于verilog 的数字钟设计过程,含有详细的代码和解释。-Based on the design process verilog digital clock contains a detailed code and explanation.
clock2
- 基于Verilog HDL及DE2开发板的数字钟设计,使用Verilog HDL实现-Based on Verilog HDL and DE2 development board of the digital clock design, use Verilog HDL to implement
Digital-clock-with-ds1302--
- 基于ds1302的数字钟设计,stc单片机,C语言,带液晶显示。-ds1302 digital clock
8051clock
- 基于8051单片机的数字钟设计方案及代码,适用于做课设的大学生-Based on 8051 digital clock design and code for class-based college students do
clock-for-nios
- 基于niosⅡ的数字钟设计,适用于多种FPGA的开发板,修改管脚可移植。-NiosⅡ digital clock design is based on, for a variety of FPGA development board, modify pin portable.
e8
- 清华大学电子系 数字钟设计实验报告(第8个实验)-Tsinghua University, Department of Electronics, digital clock design lab report (Article 8 experiments)
Digital-clock
- 利用Quartus编程软件及EDA实验板(芯片为EP1C6Q240C8)完成数字钟设计,该数字钟有显示时、分和秒的功能。-When the Quartus programming software and EDA experiment board (chip EP1C6Q240C8) complete digital clock, digital clock showing the hours, minutes and seconds functions.
dpjszz
- 使用单片机来进行数字钟设计,可以实现计时,定时,温度测量功能,还能进行校正-Digital clock using microcontroller design, can achieve timing, timing, temperature measurement function, can be corrected
Chapter16
- 数字钟设计,压缩文件里是工程实例,打开运行即可- U6570 u5B57 u949F u8BBE u8BB u8BBE u8BBE u8A
wannianli
- 2、 掌握QuartusII软件的使用; 3、 掌握计数器的设计; 4、 掌握分频器的设计; 5、 掌握时、分、秒的设计; 6、 数码管的扫描显示; 7、 掌握数字钟的整体设计(2, master the use of QuartusII software; 3. Master the design of the counter; 4. Master the design of frequency divider; 5, mastering the design of time,
KEY-shuzizhong
- 设计按键的挪位,和时钟通过按键进行加减以及复位(Design key position and clock add and subtract and reset)
shuzizhong
- 基于vhdl语言的多功能数字钟设计,硬件调试成功(Design of multi-function digital clock based on vhdl)
shuzhizhong (1)
- 数字时钟的FPGA设计,对学习FPGA有很大的帮助,希望大家能采纳(FPGA design of digital clock has great help for learning FPGA. I hope everyone can adopt it.)
Verilog的135个经典设计实例
- Verilog的135个经典设计实例,部分摘录如下:【例 9.23】可变模加法/减法计数器【例 11.7】自动售饮料机【例 11.6】“梁祝”乐曲演奏电路【例 11.5】交通灯控制器【例 11.2】4 位数字频率计控制模块【例 11.1】数字跑表【例 9.26】256×16 RAM 块【例 9.27】4 位串并转换器【例 11.8】多功能数字钟【例 11.9】电话计费器程序【例 12.13】CRC 编码【例 12.12】(7,4)循环码纠错译码器【例 12.10】(7,4)线性分组码译码器【例