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pipeline_test
- 流水线CPU,将指令的运行分为五个段,这是个五段流水线-pipeline CPU
NonPipelined_Design
- 用VHDL实现的非流水线CPU设计,可以稍加改动变成流水线设计-VHDL implementation with non-pipelined CPU design
PipelinedCPU
- 用Verilog语言实现的流水线CPU设计,大家可以参考一下。-Using Verilog design language of the line CPU, you can reference.
CPU
- 实现了简单的CPU功能 采用三级流水线和超标量-CPU functions to achieve a simple three-stage pipeline and superscalar
cpupipeline
- 流水线CPU,支持20多种指令,经过仿真测试-pipeline cpu
CPU
- 使用VHDL语言实现了一个两级流水线的CPU,-VHDL language using a two-stage pipeline of the CPU,
CPU-tool-chain-design
- 摘要:EDA技术的成熟和进步,缩短了微处理器硬件设计和综合的周期。同时,开发工具链设计的自动化,已成了高效率、高质量嵌入式微处理器设计的重要内容。本文提出了采用体系结构描述语言(ADL)实现微处理器开发工具链自动设计的有效方法。针对ADL描述流水线的局限性,进行了扩展改进,因而使改进后的ADL能用来直接描述流水线。新方法在CK幸CORE开发工具链设计中的应用表明,比用GNU工具链功效有了显著提高。-Abstract: EDA technologies mature and progress, r
32bit-RISC-CPU-IP
- 使用Verilog语言实现的RISC精简指令集CPU IP核,该CPU具有32位数据宽度,5级流水线结构和指令预判和中断处理功能,适合Verilog语言深入学习者参考。-Using the Verilog language implementation of RISC Reduced Instruction Set CPU IP cores, the CPU has a 32-bit data width, 5-stage pipeline structure and instruction p
pipeline_cpu
- 流水线cpu,pipeline_cpu,南大计算机系计算机组成原理实验-Pipeline cpu, pipeline_cpu, Nanjing University Department of Computer Science Computer Composition principle experiment
SRC
- 流水线cpu 顶层模块verilog源代码,和ALU子模块源代码-Pipelined cpu top-level module verilog source code, and the ALU sub-module source code
cpu-and-ram
- 这是一个用VHDL语言写的简单带存储器的CPU设计,不涉及流水线设计,只是简单的利用QUARTUES II里的ram-This is a simple memory write VHDL CPU design, does not involve the assembly line design, simply use the ram in QUARTUES II
the-strong-cpu-design
- 增强型CPU设计,带有PC指针与存储器,用VHDL语言写的,不含流水线设计,实现二进制灯循环亮-Enhanced CPU design, with the PC pointer memory write VHDL language, non-pipelined design to achieve binary bright light cycle
lab06
- 流水线CPU设计,最接近真实运行的学生实验课的CPU设计,是组成原理实验课大作业,包涵详细讲解-CPU design
DataCycle
- 一个计算机原理课程设计的作业,5级流水线CPU,指令集到代码均为自己设计,有最终报告文档,组建说明,并行除法,16位字长,定长指令,Verilog源代码,顶层设计图。结构简单,冲突解决方式也很简单,代码量小。-cpu cpu cpu cpu cpu cpu cpu cpu
PipelineSim
- 一个计算机原理课程设计的作业,5级流水线CPU,指令集到代码均为自己设计,有最终报告文档,组建说明,并行除法,16位字长,定长指令,Verilog源代码,顶层设计图。结构简单,冲突解决方式也很简单,代码量小。-A computer theory course design work, five pipelined CPU, instruction set to the code are design, the final report documents the formation of par
PIPELINE
- 一个计算机原理课程设计的作业,5级流水线CPU,指令集到代码均为自己设计,有最终报告文档,组建说明,并行除法,16位字长,定长指令,Verilog源代码,顶层设计图。结构简单,冲突解决方式也很简单,代码量小。-A computer theory course design work, five pipelined CPU, instruction set to the code are design, the final report documents the formation of par
PipelineCPU
- 一个计算机原理课程设计的作业,5级流水线CPU,指令集到代码均为自己设计,有最终报告文档,组建说明,并行除法,16位字长,定长指令,Verilog源代码,顶层设计图。结构简单,冲突解决方式也很简单,代码量小。-A computer theory course design work, five pipelined CPU, instruction set to the code are design, the final report documents the formation of par
x
- 某五级流水线CPU的设计原理图,含基本输入输出控制-traditional pipelined CPU design
PipelineSim
- 用verilog编写的简单流水线CPU,指令集根据DLX指令集修改而来。只支持定点操作.-Verilog prepared by the simple lines with a CPU, instruction set modified from under the DLX instruction set. Supports only fixed-point operation.
liushuixianCPU
- VHDL 流水线CPU的设计,基于Quartus II平台-VHDL design of pipelined CPU based on Quartus II platform