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doc
- VHDL：用状态机的方法实现一个8位乘法器-VHDL: state machine method used to achieve an 8-bit multiplier
2
- 里面有四个vhdl源程序 分别为状态机 三位表决器 和交通灯 优先编码器-There are four VHDL source code for the state machine, respectively, the three voting machines and traffic lights priority encoder
StateMachine
- 典型的状态机，简单的状态机可以不需要编码，也可以采用one-hot编码方式，如果状态很多时，采用格雷码，能有效避免亚稳态。-A typical state machine, a simple state machine can do without coding, can also be used one-hot encoding, if the state in many cases, the use of Gray code, can effectively avoid metastable
ram_command_reading
- 这是一个由得到的命令(地址)从RAM 中读取命令并送入一个名为FUNREG的寄存器的代码,和前面的MINICORE 可以衔接,属于mikroprogrammbar steuerwerk(可编程的控制器) 与FSM (有限状态机)构成的控制器相对-This is a get command (address) from the RAM read command and sent to a register of FUNREG code, and in front of MINICORE will
ch4ex
- 一部分简单时序逻辑电路的VHDL源代码，未包含状态机描述-Part of a simple sequential logic circuits VHDL source code, does not contain a descr iption of state machine
ch5ex
- 几个稍微深入的时序逻辑电路和状态机的VHDL代码-Several little-depth sequential logic circuit and state machine of the VHDL code
ch7ex
- 简单数字系统的VHDL代码，综合了组合，时序，和状态机-Simple digital system VHDL code, a combination of combinations, timing, and the state machine
vtbird_21
- 雷鸟车尾灯状态机,vhdl实现，对学习VHDL的同学有帮助。-Thunderbird taillights state machine, vhdl realize, the study has helped students VHDL.
VHDLdanpianji
- 本文首先对MCS8051单片机的原理进行介绍和分析；接着介绍使用EDA技术，用VHDL语言完成了8051单片机的设计工作；MCS8051单片机的CPU和数模转换器的设计运用了算术逻辑单元ALU算术运算的算法实现和控制单元的状态机；以及数模转换器的∑-△调制方法的实现。通过如上的算法实现，可以看出VHDL语言在算法级的设计上具有很多的优势和特点。使用EDA技术设计的结果既可以用FPGA／CPLD来实施验证，也可以直接做成专用集成电路(ASIC)。-VHDL
seqdet2
- 状态机实现序列检测VerilogHDL及其仿真-State machine implementation sequence VerilogHDL Detect and Simulation
UART
- 简单的uart状态机的编写，作为课程设计的资料，适于入门-UART simple state machine to prepare, as a curriculum design information, suitable for entry-
aczz
- AC算法 用指针实现 用指针指向状态机的状态变量-AC algorithm implementation using pointer with pointer to state machine of the state variables
zhuangtaiji
- 有限状态机及其设计技术是实用数字系统设计中的重要组成部分,也是实现高效可靠逻辑控制的重要途径,本程序为单进程moore型有限状态机底层设计源代码.-This procedure as a single process moore-type finite state machine underlying the design of the source code.
0723
- procedure senddata var i:integer commflg : Boolean begin commflg:=true for i:=1 to 8 do begin if not fcomm comml writecommdata(sendbutter,i) then begin Commflg=false break end end
2ddct
- 这是一款比较好的关于可编程逻辑器件的状态机源代码-This is a good comparison about programmable logic device of the state machine source code
zhuangtaiji
- 这是一个最最常用的用vhdl写的状态机，几乎哪儿都用得到-a very good state machine
actree
- 这里是我个人编写的状态机的实现的程序，-Here are my personal preparation of the state machine implementation of the procedures, 111
a
- 这里是我个人编写的状态机的实现的程序，-Here are my personal preparation of the state machine implementation of the procedures, 111
state_machine
- 基于pci的verolog hdl 状态机描述-Pci of verolog hdl-based state machine descr iption
VHDLprogram
- 含有各类寄存器，AD和DA转换器，各种算法，有限状态机，还些许组合逻辑电路设计代码-Containing various types of registers, AD and DA converters, a variety of algorithms, finite state machine, but also some combinational logic circuit design code