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clock_time
- 本文件解压后clock_time.vhd采用编程环境maxplusII,完成时间秒定时、记时,设置时间秒、声光报警等功能。-this document unpacked clock_time.vhd maxplusII use programming environment, the time for completion seconds timing, Hutchison, the set-up time seconds, sound, light, alarm functions.
[eda]vhdl
- 福州大学EDA选修课所有实验课程代码。VHDL语言描述(vhd),以及电路图(gdf)-Fuzhou University EDA optional courses in all experimental code. VHDL descr iption (vhd), and circuit (GdF)
2Dfft
- VHDL 关于2DFFT设计程序 u scinode1 ∼ scinode9.vhd: Every SCI node RTL vhdl code. The details can be seen in the following section. u 2dfft.vhd: The top module includes these scinodes and form a 3x3 SCI Torus network, and it support these sub-mo
yibutongxin
- 本程序是用VHDL语言实现异步通信控制器, hao1.vhd为主程序,hao1.scf为仿真波形-this procedure is used VHDL asynchronous communication controller, mainly hao1.vhd procedures, hao1.scf for simulation waveforms
vhd
- 基于maxplusII的EDA设计,自动绕线机的设计源程序。-maxplusII Based on the EDA design, automatic winding machine design source.
zldjkzjq
- max+plusII下编成的直流电机控制器vhd-under monument of the DC motor controller vhd
jcq
- max+plusII下的各种功能的计数器vhd-under the various functions of the counter vhd
fenpin
- 本程序是用VHDL语言,非整数分频的一个实现, fenpin.vhd为主程序-this procedure is used VHDL, non-integer frequency of a realization of the main procedures fenpin.vhd
DaFilter
- /* This program generates the DApkg.vhd file that is used to define * the DA filter core and gives its parameters and the contents of the * Distributed Arithmetic Look-up-table \"DALUT\" according to the DA algorithm-/ * This program generate
fpu_v18
- <Floating Point Unit Core> fpupack.vhd pre_norm_addsub.vhd addsub_28.vhd post_norm_addsub.vhd pre_norm_mul.vhd mul_24.vhd vcom serial_mul.vhd post_norm_mul.vhd pre_norm_div.vhd serial_div.vhd post_norm_div.vhd pre_norm_s
VHDamples
- VHD yes!about vhdl slay-Volume yes! About vhdl slay
arith_lib_standard
- 这是很全的标准库啊,不是1164.vhd,都是一些加,乘,除,平方等操作的包来的.-This is the standard for the whole ah, not 1164.vhd are some increases, multiplication, addition, operational square packages to come.
clock_top2
- 数字钟的vhd文档,个人感觉还是蛮完善的,大家可以下载了一同改进。-figures minute vhd files, individuals still feel pretty good, we can improve downloaded together.
clk_div2n
- 这是用VHDL 语言编写的参数可以直接设置的2n倍时钟分频器,在运用时,不需要阅读VHDL源代码,只需要把clk_div2n.vhd加入当前工程便可以直接调用clk_div2n.bsf。-This is the VHDL language parameters can be directly installed 2n times the clock dividers, when exercising not reading VHDL source code, clk_div2n.vhd simp
jhvhjhk
- 乒乓球游戏机实验报告实验人: 大火虎设计课题: 用VHDL设计一个乒乓球游戏机,用开关来摸拟球手及裁判,用LED来模拟乒乓球,采用每局十一球赛制,比分由七段显示器显示. 设计思路: 采用按功能分块,将整个电路分成若干子程序,利用不同的子程序来实现记分,显示,键盘控制。设计过程: 1) 对4MHZ信号进行分频,得到所需的1HZ,及七段显示器所需的频率.存为CLOCKMAKE.VHD(注:仿真时所加的信号频率比这要高。)。 2) 设计一个子程序来描述裁判,左击球手,右击球手的动作对LED显示的影响,
Bersenham_line
- 程序设计与仿真 利用FPGA驱动LCD显示中文字符“年”的VHDL程序。 --文件名:lcd_driver.vhd。 --功能:FGAD驱动LCD显示中文字符“年”。 -program design and simulation using FPGA-driven LCD display Chinese characters "," VHDL program. -- File Name : lcd_driver.vhd. -- Function : FGAD
multi4
- fulladder.vhd 一位全加器 adder.vhd 四位全加器 multi4.vhd 四位并行乘法器-fulladder.vhd a full adder adder.vhd four full adder mult i4.vhd four parallel multiplier
count16
- count16.vhd 16位BCD计数器VHDL源程序-count16.vhd 16 BCD counter VHDL source
uart-to-GPIO.vhd
- -- Filename ﹕ uart.vhd -- Author ﹕ZRtech -- Descr iption ﹕串口接收与发送程序 -- 本模块的功能是验证实现和PC机进行基本的串口通信的功能。需要在PC机上安装一个串口调试工具来验证-- 程序的功能。程序实现了一个收发一帧10个bit(即无奇偶校验位)的串口控制器,10个bit是1位起始位-- 8个数据位,1个结束位。串口的波特律由程序中定义的div_par参数决定,更改该参数可以实现相应的波-- 特率。程序当前设定的div_
ntfsclone2vhd
- Utility to convert ntfsclone "special images" to dynamic VHD virtual disks